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Administrator
SandHook
Commits
84178e6e
Commit
84178e6e
authored
May 10, 2019
by
swift_gan
Committed by
swift_gan
May 10, 2019
Browse files
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add BR
parent
8db6598a
Show whitespace changes
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Side-by-side
Showing
5 changed files
with
93 additions
and
38 deletions
+93
-38
inst_arm64.cpp
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.cpp
+28
-4
inst_arm64.h
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.h
+40
-15
inst_struct_aarch64.h
...ehook/src/main/cpp/archs/arm64/inst/inst_struct_aarch64.h
+10
-15
register_a64.h
nativehook/src/main/cpp/archs/arm64/register/register_a64.h
+8
-0
sandhook_native.cpp
nativehook/src/main/cpp/sandhook_native.cpp
+7
-4
No files found.
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.cpp
View file @
84178e6e
...
...
@@ -5,6 +5,7 @@
#include "inst_arm64.h"
#define SET_OPCODE(X) get()->opcode = OPCODE_A64(X)
#define SET_OPCODE_MULTI(X, INDEX) get()->opcode##INDEX = OPCODE_A64(X##_##INDEX)
using
namespace
SandHook
::
Asm
;
...
...
@@ -68,8 +69,8 @@ void A64_ADR_ADRP::assembler() {
A64_MOV_WIDE
::
A64_MOV_WIDE
()
{}
A64_MOV_WIDE
::
A64_MOV_WIDE
(
STRUCT_A64
(
MOV_WIDE
)
*
inst
)
:
InstructionA64
(
inst
)
{
decode
(
inst
);
A64_MOV_WIDE
::
A64_MOV_WIDE
(
STRUCT_A64
(
MOV_WIDE
)
&
inst
)
:
InstructionA64
(
&
inst
)
{
decode
(
&
inst
);
}
A64_MOV_WIDE
::
A64_MOV_WIDE
(
A64_MOV_WIDE
::
OP
op
,
RegisterA64
*
rd
,
U16
imme
,
U8
shift
)
...
...
@@ -197,8 +198,8 @@ void A64_B_COND::assembler() {
A64_TBZ_TBNZ
::
A64_TBZ_TBNZ
()
{}
A64_TBZ_TBNZ
::
A64_TBZ_TBNZ
(
STRUCT_A64
(
TBZ_TBNZ
)
*
inst
)
:
A64_INST_PC_REL
(
inst
)
{
decode
(
inst
);
A64_TBZ_TBNZ
::
A64_TBZ_TBNZ
(
STRUCT_A64
(
TBZ_TBNZ
)
&
inst
)
:
A64_INST_PC_REL
(
&
inst
)
{
decode
(
&
inst
);
}
A64_TBZ_TBNZ
::
A64_TBZ_TBNZ
(
A64_TBZ_TBNZ
::
OP
op
,
RegisterA64
*
rt
,
U32
bit
,
Off
offset
)
:
op
(
op
),
...
...
@@ -317,3 +318,26 @@ void A64_STR_IMM::assembler() {
INST_DCHECK
(
condition
,
Condition
::
nv
)
}
A64_BR_BLR_RET
::
A64_BR_BLR_RET
()
{}
A64_BR_BLR_RET
::
A64_BR_BLR_RET
(
STRUCT_A64
(
BR_BLR_RET
)
&
inst
)
:
InstructionA64
(
&
inst
)
{
decode
(
&
inst
);
}
A64_BR_BLR_RET
::
A64_BR_BLR_RET
(
A64_BR_BLR_RET
::
OP
op
,
XRegister
&
rn
)
:
op
(
op
),
rn
(
&
rn
)
{
assembler
();
}
void
A64_BR_BLR_RET
::
decode
(
A64_STRUCT_BR_BLR_RET
*
inst
)
{
rn
=
XReg
(
static_cast
<
U8
>
(
inst
->
op
));
op
=
OP
(
inst
->
rn
);
}
void
A64_BR_BLR_RET
::
assembler
()
{
SET_OPCODE_MULTI
(
BR_BLR_RET
,
1
);
SET_OPCODE_MULTI
(
BR_BLR_RET
,
2
);
SET_OPCODE_MULTI
(
BR_BLR_RET
,
3
);
get
()
->
rn
=
rn
->
getCode
();
get
()
->
op
=
op
;
}
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.h
View file @
84178e6e
...
...
@@ -15,29 +15,23 @@
#define IS_OPCODE(RAW,OP) INST_A64(OP)::is(RAW)
#define DEFINE_IS(X) \
#define DEFINE_IS_EXT(X, COND) \
inline static bool is(InstA64& inst) { \
union { \
InstA64 raw; \
STRUCT_A64(X) inst; \
} inst_test; \
inst_test.raw = inst; \
return
inst_test.inst.opcode == OPCODE_A64(X)
; \
return
COND
; \
}
#define DEFINE_IS_EXT(X, EXT_COND) \
inline static bool is(InstA64& inst) { \
union { \
InstA64 raw; \
STRUCT_A64(X) inst; \
} inst_test; \
inst_test.raw = inst; \
return inst_test.inst.opcode == OPCODE_A64(X) && EXT_COND; \
}
#define DEFINE_IS(X) DEFINE_IS_EXT(X, TEST_INST_FIELD(opcode,OPCODE_A64(X)))
#define TEST_INST_FIELD(F,V) inst_test.inst.F == V
#define TEST_INST_OPCODE(X, INDEX) inst_test.inst.opcode##INDEX == OPCODE_A64(X##_##INDEX)
namespace
SandHook
{
namespace
Asm
{
...
...
@@ -228,7 +222,7 @@ namespace SandHook {
A64_MOV_WIDE
();
A64_MOV_WIDE
(
STRUCT_A64
(
MOV_WIDE
)
*
inst
);
A64_MOV_WIDE
(
STRUCT_A64
(
MOV_WIDE
)
&
inst
);
A64_MOV_WIDE
(
A64_MOV_WIDE
::
OP
op
,
RegisterA64
*
rd
,
U16
imme
,
U8
shift
);
...
...
@@ -389,7 +383,7 @@ namespace SandHook {
A64_TBZ_TBNZ
();
A64_TBZ_TBNZ
(
STRUCT_A64
(
TBZ_TBNZ
)
*
inst
);
A64_TBZ_TBNZ
(
STRUCT_A64
(
TBZ_TBNZ
)
&
inst
);
A64_TBZ_TBNZ
(
OP
op
,
RegisterA64
*
rt
,
U32
bit
,
Off
offset
);
...
...
@@ -468,7 +462,11 @@ namespace SandHook {
A64_STR_IMM
(
Condition
condition
,
RegisterA64
&
rt
,
const
MemOperand
&
operand
);
DEFINE_IS_EXT
(
STR_IMM
,
TEST_INST_FIELD
(
unkown1_0
,
0
)
&&
TEST_INST_FIELD
(
unkown2_0
,
0
))
DEFINE_IS_EXT
(
STR_IMM
,
TEST_INST_FIELD
(
opcode
,
OPCODE_A64
(
STR_IMM
))
&&
TEST_INST_FIELD
(
unkown1_0
,
0
)
&&
TEST_INST_FIELD
(
unkown2_0
,
0
))
inline
U32
instCode
()
override
{
return
STR_x
;
}
void
decode
(
STRUCT_A64
(
STR_IMM
)
*
inst
)
override
;
...
...
@@ -492,6 +490,33 @@ namespace SandHook {
bool
index
;
};
class
INST_A64
(
BR_BLR_RET
)
:
public
InstructionA64
<
STRUCT_A64
(
BR_BLR_RET
)
>
{
public
:
enum
OP
{
BR
=
0
b00
,
BLR
=
0
b01
,
RET
=
0
b11
};
A64_BR_BLR_RET
();
A64_BR_BLR_RET
(
STRUCT_A64
(
BR_BLR_RET
)
&
inst
);
A64_BR_BLR_RET
(
OP
op
,
XRegister
&
rn
);
DEFINE_IS_EXT
(
BR_BLR_RET
,
TEST_INST_OPCODE
(
BR_BLR_RET
,
1
)
&&
TEST_INST_OPCODE
(
BR_BLR_RET
,
2
)
&&
TEST_INST_OPCODE
(
BR_BLR_RET
,
3
))
void
decode
(
A64_STRUCT_BR_BLR_RET
*
inst
)
override
;
void
assembler
()
override
;
public
:
OP
op
;
XRegister
*
rn
;
};
}
}
...
...
nativehook/src/main/cpp/archs/arm64/inst/inst_struct_aarch64.h
View file @
84178e6e
...
...
@@ -86,7 +86,6 @@ enum Extend {
SXTX
=
7
};
//ok
#define IMM_LO_W 2
#define IMM_HI_W 19
DEFINE_OPCODE
(
ADR_ADRP
,
0
b10000
)
...
...
@@ -98,8 +97,6 @@ struct STRUCT_A64(ADR_ADRP) {
InstA64
op
:
1
;
};
//ok
DEFINE_OPCODE
(
MOV_WIDE
,
0
b100101
)
struct
STRUCT_A64
(
MOV_WIDE
)
{
InstA64
rd
:
5
;
...
...
@@ -110,7 +107,6 @@ struct STRUCT_A64(MOV_WIDE) {
InstA64
sf
:
1
;
};
//ok
DEFINE_OPCODE
(
B_BL
,
0
b00101
)
struct
STRUCT_A64
(
B_BL
)
{
InstA64
imm26
:
26
;
...
...
@@ -118,7 +114,6 @@ struct STRUCT_A64(B_BL) {
InstA64
op
:
1
;
};
//ok
DEFINE_OPCODE
(
CBZ_CBNZ
,
0
b011010
)
struct
STRUCT_A64
(
CBZ_CBNZ
)
{
InstA64
rt
:
5
;
...
...
@@ -128,7 +123,6 @@ struct STRUCT_A64(CBZ_CBNZ) {
InstA64
sf
:
1
;
};
//ok
DEFINE_OPCODE
(
B_COND
,
0
b01010100
)
struct
STRUCT_A64
(
B_COND
)
{
InstA64
cond
:
4
;
...
...
@@ -137,7 +131,6 @@ struct STRUCT_A64(B_COND) {
InstA64
opcode
:
8
;
};
//ok
DEFINE_OPCODE
(
TBZ_TBNZ
,
0
b011011
)
struct
STRUCT_A64
(
TBZ_TBNZ
)
{
InstA64
rt
:
5
;
...
...
@@ -148,7 +141,6 @@ struct STRUCT_A64(TBZ_TBNZ) {
InstA64
b5
:
1
;
};
//ok
DEFINE_OPCODE
(
LDR_LIT
,
0
b011000
)
struct
STRUCT_A64
(
LDR_LIT
)
{
InstA64
rt
:
5
;
...
...
@@ -157,7 +149,6 @@ struct STRUCT_A64(LDR_LIT) {
InstA64
op
:
2
;
};
//ok
DEFINE_OPCODE
(
STR_IMM
,
0
b011
)
struct
STRUCT_A64
(
STR_IMM
)
{
InstA64
imm12
:
12
;
...
...
@@ -172,12 +163,16 @@ struct STRUCT_A64(STR_IMM) {
InstA64
cond
:
4
;
};
//ok
DEFINE_OPCODE
(
BR
,
0
b00101
)
struct
STRUCT_A64
(
BR
)
{
InstA64
imm26
:
26
;
InstA64
opcode
:
5
;
InstA64
op
:
1
;
DEFINE_OPCODE
(
BR_BLR_RET_1
,
0
b110101100
)
DEFINE_OPCODE
(
BR_BLR_RET_2
,
0
b11111000000
)
DEFINE_OPCODE
(
BR_BLR_RET_3
,
0
b00000
)
struct
STRUCT_A64
(
BR_BLR_RET
)
{
InstA64
opcode3
:
5
;
InstA64
rn
:
5
;
InstA64
opcode2
:
11
;
InstA64
op
:
2
;
InstA64
opcode1
:
9
;
};
...
...
nativehook/src/main/cpp/archs/arm64/register/register_a64.h
View file @
84178e6e
...
...
@@ -34,6 +34,14 @@ namespace SandHook {
RegisterA64
();
RegisterA64
(
U8
code
);
inline
bool
isX
()
{
return
is64Bit
();
}
inline
bool
isW
()
{
return
is32Bit
();
}
};
class
XRegister
:
public
RegisterA64
{
...
...
nativehook/src/main/cpp/sandhook_native.cpp
View file @
84178e6e
...
...
@@ -24,14 +24,17 @@ Java_com_swift_sandhook_nativehook_NativeHook_test(JNIEnv *env, jclass jclass1)
U8
s
=
sizeof
(
STRUCT_A64
(
B_BL
));
union
{
InstA64
raw
=
0x
58001001
;
STRUCT_A64
(
LDR_LIT
)
bl
;
InstA64
raw
=
0x
36A01005
;
STRUCT_A64
(
TBZ_TBNZ
)
bl
;
}
test
;
STRUCT_A64
(
LDR_LIT
)
bl
=
test
.
bl
;
if
(
IS_OPCODE
(
test
.
raw
,
TBZ_TBNZ
))
{
A64_LDR_LIT
a64ldr
(
&
bl
);
STRUCT_A64
(
TBZ_TBNZ
)
bl
=
test
.
bl
;
A64_TBZ_TBNZ
a64ldr
(
bl
);
Off
off
=
a64ldr
.
offset
;
}
}
\ No newline at end of file
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