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SandHook
Commits
1b1df47a
Commit
1b1df47a
authored
May 22, 2019
by
swift_gan
Committed by
swift_gan
May 22, 2019
Browse files
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Plain Diff
[NativeHook]add some insts
parent
5c4ddbb7
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Showing
8 changed files
with
235 additions
and
22 deletions
+235
-22
assembler_a32.cpp
.../src/main/cpp/archs/arm/arm32/assembler/assembler_a32.cpp
+78
-2
assembler_a32.h
...ok/src/main/cpp/archs/arm/arm32/assembler/assembler_a32.h
+24
-0
inst_code_arm32.h
...ehook/src/main/cpp/archs/arm/arm32/inst/inst_code_arm32.h
+2
-0
inst_struct_t16.h
...ehook/src/main/cpp/archs/arm/arm32/inst/inst_struct_t16.h
+15
-0
inst_t16.cpp
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.cpp
+51
-7
inst_t16.h
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.h
+47
-4
inst_t32.cpp
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.cpp
+13
-6
inst_t32.h
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.h
+5
-3
No files found.
nativehook/src/main/cpp/archs/arm/arm32/assembler/assembler_a32.cpp
View file @
1b1df47a
...
@@ -38,11 +38,11 @@ void AssemblerA32::Emit(Unit<Base> *unit) {
...
@@ -38,11 +38,11 @@ void AssemblerA32::Emit(Unit<Base> *unit) {
}
}
void
AssemblerA32
::
Mov
(
RegisterA32
&
rd
,
U16
imm16
)
{
void
AssemblerA32
::
Mov
(
RegisterA32
&
rd
,
U16
imm16
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
MOV_MOVT_IMM
)(
INST_T32
(
MOV_MOVT_IMM
)
::
MOV
,
&
rd
,
imm16
)));
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
MOV_MOVT_IMM
)(
INST_T32
(
MOV_MOVT_IMM
)
::
MOV
,
rd
,
imm16
)));
}
}
void
AssemblerA32
::
Movt
(
RegisterA32
&
rd
,
U16
imm16
)
{
void
AssemblerA32
::
Movt
(
RegisterA32
&
rd
,
U16
imm16
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
MOV_MOVT_IMM
)(
INST_T32
(
MOV_MOVT_IMM
)
::
MOVT
,
&
rd
,
imm16
)));
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
MOV_MOVT_IMM
)(
INST_T32
(
MOV_MOVT_IMM
)
::
MOVT
,
rd
,
imm16
)));
}
}
void
AssemblerA32
::
Mov
(
RegisterA32
&
rd
,
U32
imm32
)
{
void
AssemblerA32
::
Mov
(
RegisterA32
&
rd
,
U32
imm32
)
{
...
@@ -51,3 +51,79 @@ void AssemblerA32::Mov(RegisterA32 &rd, U32 imm32) {
...
@@ -51,3 +51,79 @@ void AssemblerA32::Mov(RegisterA32 &rd, U32 imm32) {
Mov
(
rd
,
immL
);
Mov
(
rd
,
immL
);
Movt
(
rd
,
immH
);
Movt
(
rd
,
immH
);
}
}
void
AssemblerA32
::
Ldr
(
RegisterA32
&
rt
,
Label
*
label
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_LIT
)(
INST_T32
(
LDR_LIT
)
::
LDR
,
rt
,
*
label
)));
}
void
AssemblerA32
::
Ldrb
(
RegisterA32
&
rt
,
Label
*
label
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_LIT
)(
INST_T32
(
LDR_LIT
)
::
LDRB
,
rt
,
*
label
)));
}
void
AssemblerA32
::
Ldrh
(
RegisterA32
&
rt
,
Label
*
label
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_LIT
)(
INST_T32
(
LDR_LIT
)
::
LDRH
,
rt
,
*
label
)));
}
void
AssemblerA32
::
Ldr
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
)
{
if
(
operand
.
addr_mode
==
Offset
&&
operand
.
offset
>=
0
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_UIMM
)(
rt
,
*
operand
.
rn
,
operand
.
addr_mode
)));
}
else
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_IMM
)(
INST_T32
(
LDR_IMM
)
::
LDR
,
rt
,
operand
)));
}
}
void
AssemblerA32
::
Ldrb
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_IMM
)(
INST_T32
(
LDR_IMM
)
::
LDRB
,
rt
,
operand
)));
}
void
AssemblerA32
::
Ldrh
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_IMM
)(
INST_T32
(
LDR_IMM
)
::
LDRH
,
rt
,
operand
)));
}
void
AssemblerA32
::
Ldrsb
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_IMM
)(
INST_T32
(
LDR_IMM
)
::
LDRSB
,
rt
,
operand
)));
}
void
AssemblerA32
::
Ldrsh
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
LDR_IMM
)(
INST_T32
(
LDR_IMM
)
::
LDRSH
,
rt
,
operand
)));
}
void
AssemblerA32
::
B
(
Label
*
label
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
B32
)(
INST_T32
(
B32
)
::
B
,
INST_T32
(
B32
)
::
arm
,
*
label
)));
}
void
AssemblerA32
::
Bl
(
Label
*
label
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
B32
)(
INST_T32
(
B32
)
::
BL
,
INST_T32
(
B32
)
::
arm
,
*
label
)));
}
void
AssemblerA32
::
Blx
(
Label
*
label
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
B32
)(
INST_T32
(
B32
)
::
BL
,
INST_T32
(
B32
)
::
thumb
,
*
label
)));
}
void
AssemblerA32
::
Bx
(
Label
*
label
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T32
(
B32
)(
INST_T32
(
B32
)
::
B
,
INST_T32
(
B32
)
::
thumb
,
*
label
)));
}
void
AssemblerA32
::
Mov
(
RegisterA32
&
rd
,
RegisterA32
&
rm
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T16
(
MOV_REG
)(
rd
,
rm
)));
}
void
AssemblerA32
::
Bx
(
RegisterA32
&
rm
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T16
(
BX_BLX
)(
INST_T16
(
BX_BLX
)
::
BX
,
rm
)));
}
void
AssemblerA32
::
Blx
(
RegisterA32
&
rm
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T16
(
BX_BLX
)(
INST_T16
(
BX_BLX
)
::
BLX
,
rm
)));
}
void
AssemblerA32
::
B
(
Condition
condition
,
Label
*
label
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T16
(
B_COND
)(
condition
,
*
label
)));
}
void
AssemblerA32
::
Add
(
RegisterA32
&
rdn
,
U8
imm8
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T16
(
ADD_IMM_RDN
)(
&
rdn
,
imm8
)));
}
void
AssemblerA32
::
Add
(
RegisterA32
&
rd
,
RegisterA32
&
rn
,
RegisterA32
&
rm
)
{
Emit
(
reinterpret_cast
<
Unit
<
Base
>*>
(
new
INST_T16
(
ADD_REG
)(
&
rd
,
&
rn
,
&
rm
)));
}
nativehook/src/main/cpp/archs/arm/arm32/assembler/assembler_a32.h
View file @
1b1df47a
...
@@ -32,6 +32,30 @@ namespace SandHook {
...
@@ -32,6 +32,30 @@ namespace SandHook {
void
Movt
(
RegisterA32
&
rd
,
U16
imm16
);
void
Movt
(
RegisterA32
&
rd
,
U16
imm16
);
void
Mov
(
RegisterA32
&
rd
,
U32
imm32
);
void
Mov
(
RegisterA32
&
rd
,
U32
imm32
);
void
Mov
(
RegisterA32
&
rd
,
RegisterA32
&
rm
);
void
Ldr
(
RegisterA32
&
rt
,
Label
*
label
);
void
Ldrb
(
RegisterA32
&
rt
,
Label
*
label
);
void
Ldrh
(
RegisterA32
&
rt
,
Label
*
label
);
void
Ldr
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
);
void
Ldrb
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
);
void
Ldrh
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
);
void
Ldrsb
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
);
void
Ldrsh
(
RegisterA32
&
rt
,
const
MemOperand
&
operand
);
void
B
(
Label
*
label
);
void
Bl
(
Label
*
label
);
void
Blx
(
Label
*
label
);
void
Bx
(
Label
*
label
);
void
Blx
(
RegisterA32
&
rm
);
void
Bx
(
RegisterA32
&
rm
);
void
B
(
Condition
condition
,
Label
*
label
);
void
Add
(
RegisterA32
&
rdn
,
U8
imm8
);
void
Add
(
RegisterA32
&
rd
,
RegisterA32
&
rn
,
RegisterA32
&
rm
);
public
:
public
:
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_code_arm32.h
View file @
1b1df47a
...
@@ -23,7 +23,9 @@ enum class InstCodeT16 {
...
@@ -23,7 +23,9 @@ enum class InstCodeT16 {
ADD_IMM_RDN
,
ADD_IMM_RDN
,
//rn = pc
//rn = pc
ADR
,
ADR
,
ADD_REG
,
CMP_REG
,
CMP_REG
,
CMP_REG_EXT
,
MOV_IMM
,
MOV_IMM
,
MOV_REG
,
MOV_REG
,
};
};
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_struct_t16.h
View file @
1b1df47a
...
@@ -100,6 +100,14 @@ DEFINE_STRUCT_T16(CMP_REG) {
...
@@ -100,6 +100,14 @@ DEFINE_STRUCT_T16(CMP_REG) {
DATA_PROC_FIELDS
DATA_PROC_FIELDS
};
};
DEFINE_OPCODE_T16
(
CMP_REG_EXT
,
0
b1010
)
DEFINE_STRUCT_T16
(
CMP_REG_EXT
)
{
InstT16
rn
:
4
;
InstT16
rm
:
4
;
InstT16
N
:
1
;
InstT16
opcode
:
8
;
};
DEFINE_OPCODE_T16
(
MOV_REG
,
0
b10
)
DEFINE_OPCODE_T16
(
MOV_REG
,
0
b10
)
DEFINE_STRUCT_T16
(
MOV_REG
)
{
DEFINE_STRUCT_T16
(
MOV_REG
)
{
InstT16
rd
:
T16_REG_WIDE
;
InstT16
rd
:
T16_REG_WIDE
;
...
@@ -115,6 +123,13 @@ DEFINE_STRUCT_T16(MOV_IMM) {
...
@@ -115,6 +123,13 @@ DEFINE_STRUCT_T16(MOV_IMM) {
InstT16
opcode
:
5
;
InstT16
opcode
:
5
;
};
};
DEFINE_OPCODE_T16
(
ADD_REG
,
0
b0001100
)
DEFINE_STRUCT_T16
(
ADD_REG
)
{
InstT16
rd
:
T16_REG_WIDE
;
InstT16
rn
:
T16_REG_WIDE
;
InstT16
rm
:
T16_REG_WIDE
;
InstT16
opcode
:
7
;
};
#endif //SANDHOOK_NH_INST_STRUCT_T16_H
#endif //SANDHOOK_NH_INST_STRUCT_T16_H
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.cpp
View file @
1b1df47a
...
@@ -184,16 +184,18 @@ T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(T16_STRUCT_ADD_IMM_RDN *inst) : InstructionT16(
...
@@ -184,16 +184,18 @@ T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(T16_STRUCT_ADD_IMM_RDN *inst) : InstructionT16(
}
}
T16_ADD_IMM_RDN
::
T16_ADD_IMM_RDN
(
RegisterA32
*
rdn
,
S32
imm32
)
:
rdn
(
rdn
),
imm32
(
imm32
)
{}
T16_ADD_IMM_RDN
::
T16_ADD_IMM_RDN
(
RegisterA32
*
rdn
,
U8
imm8
)
:
rdn
(
rdn
),
imm8
(
imm8
)
{}
void
T16_ADD_IMM_RDN
::
decode
(
T16_STRUCT_ADD_IMM_RDN
*
inst
)
{
void
T16_ADD_IMM_RDN
::
decode
(
T16_STRUCT_ADD_IMM_RDN
*
inst
)
{
imm32
=
inst
->
imm8
;
rdn
=
Reg
(
inst
->
rdn
);
imm8
=
inst
->
imm8
;
}
}
void
T16_ADD_IMM_RDN
::
assembler
()
{
void
T16_ADD_IMM_RDN
::
assembler
()
{
SET_OPCODE
(
ADD_IMM_RDN
);
SET_OPCODE
(
ADD_IMM_RDN
);
get
()
->
imm8
=
imm32
;
get
()
->
imm8
=
imm8
;
get
()
->
rdn
=
rdn
->
getCode
();
}
}
...
@@ -252,10 +254,6 @@ void T16_CMP_REG::assembler() {
...
@@ -252,10 +254,6 @@ void T16_CMP_REG::assembler() {
ENCODE_RN
;
ENCODE_RN
;
}
}
bool
T16_CMP_REG
::
pcRelate
()
{
return
rn
==
&
PC
||
rm
==
&
PC
;
}
//MOV REG
//MOV REG
...
@@ -284,3 +282,49 @@ bool T16_MOV_REG::pcRelate() {
...
@@ -284,3 +282,49 @@ bool T16_MOV_REG::pcRelate() {
return
rd
==
&
PC
||
rm
==
&
PC
;
return
rd
==
&
PC
||
rm
==
&
PC
;
}
}
T16_ADD_REG
::
T16_ADD_REG
()
{}
T16_ADD_REG
::
T16_ADD_REG
(
T16_STRUCT_ADD_REG
*
inst
)
:
InstructionT16
(
inst
)
{
decode
(
inst
);
}
T16_ADD_REG
::
T16_ADD_REG
(
RegisterA32
*
rd
,
RegisterA32
*
rn
,
RegisterA32
*
rm
)
:
rd
(
rd
),
rn
(
rn
),
rm
(
rm
)
{}
void
T16_ADD_REG
::
decode
(
T16_STRUCT_ADD_REG
*
inst
)
{
DECODE_RD
(
Reg
);
DECODE_RN
(
Reg
);
DECODE_RM
(
Reg
);
}
void
T16_ADD_REG
::
assembler
()
{
SET_OPCODE
(
ADD_REG
);
INST_ASSERT
(
rd
->
getCode
()
>
7
);
INST_ASSERT
(
rn
->
getCode
()
>
7
);
INST_ASSERT
(
rm
->
getCode
()
>
7
);
ENCODE_RD
;
ENCODE_RN
;
ENCODE_RM
;
}
T16_CMP_REG_EXT
::
T16_CMP_REG_EXT
(
T16_STRUCT_CMP_REG_EXT
*
inst
)
:
InstructionT16
(
inst
)
{
decode
(
inst
);
}
T16_CMP_REG_EXT
::
T16_CMP_REG_EXT
(
RegisterA32
*
rn
,
RegisterA32
*
rm
)
:
rn
(
rn
),
rm
(
rm
)
{}
void
T16_CMP_REG_EXT
::
decode
(
T16_STRUCT_CMP_REG_EXT
*
inst
)
{
rn
=
Reg
(
COMBINE
(
inst
->
N
,
inst
->
rn
,
3
));
DECODE_RM
(
Reg
);
}
void
T16_CMP_REG_EXT
::
assembler
()
{
SET_OPCODE
(
CMP_REG_EXT
);
ENCODE_RM
;
get
()
->
rn
=
BITS
(
rn
->
getCode
(),
0
,
2
);
get
()
->
N
=
BIT
(
rn
->
getCode
(),
3
);
}
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.h
View file @
1b1df47a
...
@@ -250,7 +250,7 @@ namespace SandHook {
...
@@ -250,7 +250,7 @@ namespace SandHook {
public
:
public
:
T16_ADD_IMM_RDN
(
T16_STRUCT_ADD_IMM_RDN
*
inst
);
T16_ADD_IMM_RDN
(
T16_STRUCT_ADD_IMM_RDN
*
inst
);
T16_ADD_IMM_RDN
(
RegisterA32
*
rdn
,
S32
imm32
);
T16_ADD_IMM_RDN
(
RegisterA32
*
rdn
,
U8
imm8
);
void
decode
(
T16_STRUCT_ADD_IMM_RDN
*
inst
)
override
;
void
decode
(
T16_STRUCT_ADD_IMM_RDN
*
inst
)
override
;
...
@@ -258,7 +258,7 @@ namespace SandHook {
...
@@ -258,7 +258,7 @@ namespace SandHook {
public
:
public
:
RegisterA32
*
rdn
;
RegisterA32
*
rdn
;
S32
imm32
;
U8
imm8
;
};
};
class
INST_T16
(
ADR
)
:
public
T16_INST_PC_REL
<
STRUCT_T16
(
ADR
)
>
{
class
INST_T16
(
ADR
)
:
public
T16_INST_PC_REL
<
STRUCT_T16
(
ADR
)
>
{
...
@@ -304,8 +304,6 @@ namespace SandHook {
...
@@ -304,8 +304,6 @@ namespace SandHook {
void
assembler
()
override
;
void
assembler
()
override
;
bool
pcRelate
()
override
;
public
:
public
:
RegisterA32
*
rm
;
RegisterA32
*
rm
;
RegisterA32
*
rn
;
RegisterA32
*
rn
;
...
@@ -334,6 +332,51 @@ namespace SandHook {
...
@@ -334,6 +332,51 @@ namespace SandHook {
RegisterA32
*
rm
;
RegisterA32
*
rm
;
};
};
class
INST_T16
(
ADD_REG
)
:
public
InstructionT16
<
STRUCT_T16
(
ADD_REG
)
>
{
public
:
T16_ADD_REG
();
T16_ADD_REG
(
T16_STRUCT_ADD_REG
*
inst
);
T16_ADD_REG
(
RegisterA32
*
rd
,
RegisterA32
*
rn
,
RegisterA32
*
rm
);
DEFINE_IS
(
ADD_REG
)
DEFINE_INST_CODE
(
ADD_REG
)
void
decode
(
T16_STRUCT_ADD_REG
*
inst
)
override
;
void
assembler
()
override
;
public
:
RegisterA32
*
rd
;
RegisterA32
*
rn
;
RegisterA32
*
rm
;
};
class
INST_T16
(
CMP_REG_EXT
)
:
public
InstructionT16
<
STRUCT_T16
(
CMP_REG_EXT
)
>
{
public
:
T16_CMP_REG_EXT
(
T16_STRUCT_CMP_REG_EXT
*
inst
);
T16_CMP_REG_EXT
(
RegisterA32
*
rn
,
RegisterA32
*
rm
);
DEFINE_IS
(
CMP_REG_EXT
)
DEFINE_INST_CODE
(
CMP_REG_EXT
)
void
decode
(
T16_STRUCT_CMP_REG_EXT
*
inst
)
override
;
void
assembler
()
override
;
public
:
RegisterA32
*
rn
;
RegisterA32
*
rm
;
};
}
}
}
}
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.cpp
View file @
1b1df47a
...
@@ -89,9 +89,16 @@ void T32_LDR_UIMM::assembler() {
...
@@ -89,9 +89,16 @@ void T32_LDR_UIMM::assembler() {
T32_LDR_LIT
::
T32_LDR_LIT
()
{}
T32_LDR_LIT
::
T32_LDR_LIT
()
{}
T32_LDR_LIT
::
T32_LDR_LIT
(
T32_STRUCT_LDR_LIT
*
inst
)
:
T32_INST_PC_REL
(
inst
)
{}
T32_LDR_LIT
::
T32_LDR_LIT
(
T32_STRUCT_LDR_LIT
*
inst
)
:
T32_INST_PC_REL
(
inst
)
{
decode
(
inst
);
}
T32_LDR_LIT
::
T32_LDR_LIT
(
OP
op
,
RegisterA32
&
rt
,
Off
offset
)
:
op
(
op
),
rt
(
&
rt
),
offset
(
offset
)
{}
T32_LDR_LIT
::
T32_LDR_LIT
(
RegisterA32
&
rt
,
Off
offset
)
:
rt
(
&
rt
),
offset
(
offset
)
{}
T32_LDR_LIT
::
T32_LDR_LIT
(
OP
op
,
RegisterA32
&
rt
,
Label
&
label
)
:
op
(
op
),
rt
(
&
rt
)
{
bindLabel
(
label
);
}
Off
T32_LDR_LIT
::
getImmPCOffset
()
{
Off
T32_LDR_LIT
::
getImmPCOffset
()
{
return
get
()
->
U
==
add
?
get
()
->
imm12
:
-
get
()
->
imm12
;
return
get
()
->
U
==
add
?
get
()
->
imm12
:
-
get
()
->
imm12
;
...
@@ -122,8 +129,8 @@ T32_MOV_MOVT_IMM::T32_MOV_MOVT_IMM() {}
...
@@ -122,8 +129,8 @@ T32_MOV_MOVT_IMM::T32_MOV_MOVT_IMM() {}
T32_MOV_MOVT_IMM
::
T32_MOV_MOVT_IMM
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
)
:
InstructionT32
(
inst
)
{}
T32_MOV_MOVT_IMM
::
T32_MOV_MOVT_IMM
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
)
:
InstructionT32
(
inst
)
{}
T32_MOV_MOVT_IMM
::
T32_MOV_MOVT_IMM
(
T32_MOV_MOVT_IMM
::
OP
op
,
RegisterA32
*
rd
,
U16
imm16
)
:
op
(
op
),
T32_MOV_MOVT_IMM
::
T32_MOV_MOVT_IMM
(
T32_MOV_MOVT_IMM
::
OP
op
,
RegisterA32
&
rd
,
U16
imm16
)
:
op
(
op
),
rd
(
rd
),
rd
(
&
rd
),
imm16
(
imm16
)
{}
imm16
(
imm16
)
{}
void
T32_MOV_MOVT_IMM
::
decode
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
)
{
void
T32_MOV_MOVT_IMM
::
decode
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
)
{
...
@@ -148,8 +155,8 @@ T32_LDR_IMM::T32_LDR_IMM(T32_STRUCT_LDR_IMM *inst) : InstructionT32(inst) {
...
@@ -148,8 +155,8 @@ T32_LDR_IMM::T32_LDR_IMM(T32_STRUCT_LDR_IMM *inst) : InstructionT32(inst) {
decode
(
inst
);
decode
(
inst
);
}
}
T32_LDR_IMM
::
T32_LDR_IMM
(
T32_LDR_IMM
::
OP
op
,
RegisterA32
*
rt
,
const
MemOperand
&
operand
)
:
op
(
op
),
T32_LDR_IMM
::
T32_LDR_IMM
(
T32_LDR_IMM
::
OP
op
,
RegisterA32
&
rt
,
const
MemOperand
&
operand
)
:
op
(
op
),
rt
(
rt
),
rt
(
&
rt
),
operand
(
operand
)
{}
operand
(
operand
)
{}
void
T32_LDR_IMM
::
decode
(
T32_STRUCT_LDR_IMM
*
inst
)
{
void
T32_LDR_IMM
::
decode
(
T32_STRUCT_LDR_IMM
*
inst
)
{
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.h
View file @
1b1df47a
...
@@ -177,7 +177,9 @@ namespace SandHook {
...
@@ -177,7 +177,9 @@ namespace SandHook {
T32_LDR_LIT
(
T32_STRUCT_LDR_LIT
*
inst
);
T32_LDR_LIT
(
T32_STRUCT_LDR_LIT
*
inst
);
T32_LDR_LIT
(
RegisterA32
&
rt
,
Off
offset
);
T32_LDR_LIT
(
OP
op
,
RegisterA32
&
rt
,
Off
offset
);
T32_LDR_LIT
(
OP
op
,
RegisterA32
&
rt
,
Label
&
label
);
DEFINE_IS
(
LDR_LIT
)
DEFINE_IS
(
LDR_LIT
)
...
@@ -208,7 +210,7 @@ namespace SandHook {
...
@@ -208,7 +210,7 @@ namespace SandHook {
T32_MOV_MOVT_IMM
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
);
T32_MOV_MOVT_IMM
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
);
T32_MOV_MOVT_IMM
(
OP
op
,
RegisterA32
*
rd
,
U16
imm16
);
T32_MOV_MOVT_IMM
(
OP
op
,
RegisterA32
&
rd
,
U16
imm16
);
DEFINE_IS_EXT
(
MOV_MOVT_IMM
,
TEST_INST_OPCODE
(
MOV_MOVT_IMM
,
1
)
&&
TEST_INST_OPCODE
(
MOV_MOVT_IMM
,
2
))
DEFINE_IS_EXT
(
MOV_MOVT_IMM
,
TEST_INST_OPCODE
(
MOV_MOVT_IMM
,
1
)
&&
TEST_INST_OPCODE
(
MOV_MOVT_IMM
,
2
))
...
@@ -238,7 +240,7 @@ namespace SandHook {
...
@@ -238,7 +240,7 @@ namespace SandHook {
T32_LDR_IMM
(
T32_STRUCT_LDR_IMM
*
inst
);
T32_LDR_IMM
(
T32_STRUCT_LDR_IMM
*
inst
);
T32_LDR_IMM
(
OP
op
,
RegisterA32
*
rt
,
const
MemOperand
&
operand
);
T32_LDR_IMM
(
OP
op
,
RegisterA32
&
rt
,
const
MemOperand
&
operand
);
DEFINE_IS_EXT
(
LDR_IMM
,
TEST_INST_OPCODE
(
LDR_IMM
,
1
)
&&
TEST_INST_OPCODE
(
LDR_IMM
,
2
))
DEFINE_IS_EXT
(
LDR_IMM
,
TEST_INST_OPCODE
(
LDR_IMM
,
1
)
&&
TEST_INST_OPCODE
(
LDR_IMM
,
2
))
...
...
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