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SandHook
Commits
60c8b84a
Commit
60c8b84a
authored
May 21, 2019
by
swift_gan
Committed by
swift_gan
May 21, 2019
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Plain Diff
[NativeHook]done Thumb2 insts struct
parent
422f080b
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Showing
5 changed files
with
174 additions
and
0 deletions
+174
-0
arm32_base.h
nativehook/src/main/cpp/archs/arm/arm32/inst/arm32_base.h
+15
-0
inst_struct_t32.h
...ehook/src/main/cpp/archs/arm/arm32/inst/inst_struct_t32.h
+17
-0
inst_t16.cpp
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.cpp
+2
-0
inst_t32.cpp
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.cpp
+83
-0
inst_t32.h
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.h
+57
-0
No files found.
nativehook/src/main/cpp/archs/arm/arm32/inst/arm32_base.h
View file @
60c8b84a
...
@@ -8,6 +8,7 @@
...
@@ -8,6 +8,7 @@
#include <ostream>
#include <ostream>
#include "arm_base.h"
#include "arm_base.h"
#include "register_list_a32.h"
#include "register_list_a32.h"
#include "instruction.h"
#define DECODE_OFFSET(bits, ext) signExtend32(bits + ext, COMBINE(get()->imm##bits, 0, ext))
#define DECODE_OFFSET(bits, ext) signExtend32(bits + ext, COMBINE(get()->imm##bits, 0, ext))
#define ENCODE_OFFSET(bits, ext) get()->imm##bits = TruncateToUint##bits(offset >> ext)
#define ENCODE_OFFSET(bits, ext) get()->imm##bits = TruncateToUint##bits(offset >> ext)
...
@@ -22,6 +23,10 @@ namespace SandHook {
...
@@ -22,6 +23,10 @@ namespace SandHook {
class
MemOperand
{
class
MemOperand
{
public
:
public
:
explicit
MemOperand
()
:
rn
(
&
UnknowRegiser
),
rm
(
&
UnknowRegiser
),
offset
(
0
),
addr_mode
(
Offset
)
{}
explicit
MemOperand
(
RegisterA32
*
rn
,
S32
offset
=
0
,
AddrMode
am
=
Offset
)
explicit
MemOperand
(
RegisterA32
*
rn
,
S32
offset
=
0
,
AddrMode
am
=
Offset
)
:
rn
(
rn
),
rm
(
&
UnknowRegiser
),
offset
(
offset
),
addr_mode
(
am
)
{}
:
rn
(
rn
),
rm
(
&
UnknowRegiser
),
offset
(
offset
),
addr_mode
(
am
)
{}
...
@@ -146,6 +151,16 @@ namespace SandHook {
...
@@ -146,6 +151,16 @@ namespace SandHook {
return
((
code
&
0xF000
)
==
0xF000
)
||
((
code
&
0xF800
)
==
0xE800
);
return
((
code
&
0xF000
)
==
0xF000
)
||
((
code
&
0xF800
)
==
0xE800
);
}
}
inline
void
*
getThumbCodeAddress
(
void
*
code
)
{
Addr
addr
=
reinterpret_cast
<
Addr
>
(
code
)
&
(
~
0x1
);
return
reinterpret_cast
<
void
*>
(
addr
);
}
inline
void
*
getThumbPC
(
void
*
code
)
{
Addr
addr
=
reinterpret_cast
<
Addr
>
(
code
)
&
(
~
0x1
);
return
reinterpret_cast
<
void
*>
(
addr
+
1
);
}
std
::
ostream
&
operator
<<
(
std
::
ostream
&
os
,
RegisterList
registers
);
std
::
ostream
&
operator
<<
(
std
::
ostream
&
os
,
RegisterList
registers
);
}
}
}
}
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_struct_t32.h
View file @
60c8b84a
...
@@ -48,6 +48,22 @@ DEFINE_STRUCT_T32(LDR_UIMM) {
...
@@ -48,6 +48,22 @@ DEFINE_STRUCT_T32(LDR_UIMM) {
InstT32
opcode
:
12
;
InstT32
opcode
:
12
;
};
};
//ldr imm T4
DEFINE_OPCODE_T32
(
LDR_IMM_1
,
0
b11111000
)
DEFINE_OPCODE_T32
(
LDR_IMM_2
,
0
b1
)
DEFINE_STRUCT_T32
(
LDR_IMM
)
{
InstT32
imm8
:
8
;
InstT32
W
:
1
;
InstT32
U
:
1
;
InstT32
P
:
1
;
InstT32
opcode2
:
1
;
InstT32
rt
:
T32_REG_WIDE
;
InstT32
rn
:
T32_REG_WIDE
;
InstT32
op
:
4
;
InstT32
opcode1
:
8
;
};
DEFINE_OPCODE_T32
(
MOV_MOVT_IMM_1
,
0
b11110
)
DEFINE_OPCODE_T32
(
MOV_MOVT_IMM_1
,
0
b11110
)
DEFINE_OPCODE_T32
(
MOV_MOVT_IMM_2
,
0
b0
)
DEFINE_OPCODE_T32
(
MOV_MOVT_IMM_2
,
0
b0
)
DEFINE_STRUCT_T32
(
MOV_MOVT_IMM
)
{
DEFINE_STRUCT_T32
(
MOV_MOVT_IMM
)
{
...
@@ -62,4 +78,5 @@ DEFINE_STRUCT_T32(MOV_MOVT_IMM) {
...
@@ -62,4 +78,5 @@ DEFINE_STRUCT_T32(MOV_MOVT_IMM) {
};
};
#endif //SANDHOOK_NH_INST_STRUCT_T32_H
#endif //SANDHOOK_NH_INST_STRUCT_T32_H
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.cpp
View file @
60c8b84a
...
@@ -276,6 +276,8 @@ void T16_MOV_REG::assembler() {
...
@@ -276,6 +276,8 @@ void T16_MOV_REG::assembler() {
SET_BASE_OPCODE
(
DATA_PROC
);
SET_BASE_OPCODE
(
DATA_PROC
);
SET_OPCODE
(
MOV_REG
);
SET_OPCODE
(
MOV_REG
);
ENCODE_RM
;
ENCODE_RM
;
get
()
->
rd
=
BITS
(
rd
->
getCode
(),
0
,
2
);
get
()
->
D
=
BIT
(
rd
->
getCode
(),
3
);
}
}
bool
T16_MOV_REG
::
pcRelate
()
{
bool
T16_MOV_REG
::
pcRelate
()
{
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.cpp
View file @
60c8b84a
...
@@ -115,3 +115,86 @@ void T32_LDR_LIT::assembler() {
...
@@ -115,3 +115,86 @@ void T32_LDR_LIT::assembler() {
get
()
->
imm12
=
static_cast
<
InstT32
>
(
-
offset
);
get
()
->
imm12
=
static_cast
<
InstT32
>
(
-
offset
);
}
}
}
}
T32_MOV_MOVT_IMM
::
T32_MOV_MOVT_IMM
()
{}
T32_MOV_MOVT_IMM
::
T32_MOV_MOVT_IMM
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
)
:
InstructionT32
(
inst
)
{}
T32_MOV_MOVT_IMM
::
T32_MOV_MOVT_IMM
(
T32_MOV_MOVT_IMM
::
OP
op
,
RegisterA32
*
rd
,
U16
imm16
)
:
op
(
op
),
rd
(
rd
),
imm16
(
imm16
)
{}
void
T32_MOV_MOVT_IMM
::
decode
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
)
{
DECODE_RD
(
Reg
);
U16
imm4i
=
COMBINE
(
inst
->
imm4
,
inst
->
i
,
1
);
U16
imm38
=
COMBINE
(
inst
->
imm3
,
inst
->
imm8
,
8
);
imm16
=
COMBINE
(
imm4i
,
imm38
,
11
);
}
void
T32_MOV_MOVT_IMM
::
assembler
()
{
SET_OPCODE_MULTI
(
MOV_MOVT_IMM
,
1
);
SET_OPCODE_MULTI
(
MOV_MOVT_IMM
,
2
);
ENCODE_RD
;
get
()
->
imm8
=
BITS
(
imm16
,
0
,
7
);
get
()
->
imm3
=
BITS
(
imm16
,
8
,
10
);
get
()
->
i
=
BIT
(
imm16
,
11
);
get
()
->
imm4
=
BITS
(
imm16
,
12
,
15
);
}
T32_LDR_IMM
::
T32_LDR_IMM
(
T32_STRUCT_LDR_IMM
*
inst
)
:
InstructionT32
(
inst
)
{
decode
(
inst
);
}
T32_LDR_IMM
::
T32_LDR_IMM
(
T32_LDR_IMM
::
OP
op
,
RegisterA32
*
rt
,
const
MemOperand
&
operand
)
:
op
(
op
),
rt
(
rt
),
operand
(
operand
)
{}
void
T32_LDR_IMM
::
decode
(
T32_STRUCT_LDR_IMM
*
inst
)
{
DECODE_OP
;
DECODE_RT
(
Reg
);
operand
.
rn
=
Reg
(
static_cast
<
U8
>
(
inst
->
rn
));
if
(
inst
->
P
==
1
&&
inst
->
U
==
0
&&
inst
->
W
==
0
)
{
operand
.
addr_mode
=
Offset
;
}
else
if
(
inst
->
P
==
0
&&
inst
->
W
==
1
)
{
operand
.
addr_mode
=
PostIndex
;
}
else
if
(
inst
->
P
==
1
&&
inst
->
W
==
1
)
{
operand
.
addr_mode
=
PreIndex
;
}
else
{
valid
=
false
;
}
operand
.
offset
=
inst
->
U
==
0
?
-
inst
->
imm8
:
inst
->
imm8
;
}
void
T32_LDR_IMM
::
assembler
()
{
SET_OPCODE_MULTI
(
LDR_IMM
,
1
);
SET_OPCODE_MULTI
(
LDR_IMM
,
2
);
ENCODE_OP
;
get
()
->
rn
=
operand
.
rn
->
getCode
();
if
(
operand
.
offset
<
0
)
{
get
()
->
imm8
=
static_cast
<
InstT32
>
(
-
operand
.
offset
);
get
()
->
U
=
0
;
}
else
{
get
()
->
imm8
=
static_cast
<
InstT32
>
(
operand
.
offset
);
get
()
->
U
=
1
;
}
switch
(
operand
.
addr_mode
)
{
case
Offset
:
get
()
->
P
=
1
;
get
()
->
U
=
0
;
get
()
->
W
=
0
;
break
;
case
PostIndex
:
get
()
->
P
=
0
;
get
()
->
W
=
1
;
break
;
case
PreIndex
:
get
()
->
P
=
1
;
get
()
->
W
=
1
;
break
;
default
:
valid
=
false
;
}
}
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.h
View file @
60c8b84a
...
@@ -6,6 +6,7 @@
...
@@ -6,6 +6,7 @@
#define SANDHOOK_INST_T32_H
#define SANDHOOK_INST_T32_H
#include "arm_base.h"
#include "arm_base.h"
#include "arm32_base.h"
#include "register_list_a32.h"
#include "register_list_a32.h"
#include "inst_struct_t16.h"
#include "inst_struct_t16.h"
#include "inst_code_arm32.h"
#include "inst_code_arm32.h"
...
@@ -195,7 +196,63 @@ namespace SandHook {
...
@@ -195,7 +196,63 @@ namespace SandHook {
};
};
class
INST_T32
(
MOV_MOVT_IMM
)
:
public
InstructionT32
<
STRUCT_T32
(
MOV_MOVT_IMM
)
>
{
public
:
enum
OP
{
MOV
=
0
b100100
,
MOVT
=
0
b101100
};
T32_MOV_MOVT_IMM
();
T32_MOV_MOVT_IMM
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
);
T32_MOV_MOVT_IMM
(
OP
op
,
RegisterA32
*
rd
,
U16
imm16
);
DEFINE_IS_EXT
(
MOV_MOVT_IMM
,
TEST_INST_OPCODE
(
MOV_MOVT_IMM
,
1
)
&&
TEST_INST_OPCODE
(
MOV_MOVT_IMM
,
2
))
DEFINE_INST_CODE
(
MOV_MOVT_IMM
)
void
decode
(
T32_STRUCT_MOV_MOVT_IMM
*
inst
)
override
;
void
assembler
()
override
;
public
:
OP
op
;
RegisterA32
*
rd
;
U16
imm16
;
};
class
INST_T32
(
LDR_IMM
)
:
public
InstructionT32
<
STRUCT_T32
(
LDR_IMM
)
>
{
public
:
enum
OP
{
LDR
=
0
b0101
,
LDRB
=
0
b1001
,
LDRH
=
0
b1011
,
LDRSB
=
0
b0001
,
LDRSH
=
0
b0011
};
T32_LDR_IMM
(
T32_STRUCT_LDR_IMM
*
inst
);
T32_LDR_IMM
(
OP
op
,
RegisterA32
*
rt
,
const
MemOperand
&
operand
);
DEFINE_IS_EXT
(
LDR_IMM
,
TEST_INST_OPCODE
(
LDR_IMM
,
1
)
&&
TEST_INST_OPCODE
(
LDR_IMM
,
2
))
DEFINE_INST_CODE
(
LDR_IMM
)
void
decode
(
T32_STRUCT_LDR_IMM
*
inst
)
override
;
void
assembler
()
override
;
public
:
OP
op
;
RegisterA32
*
rt
;
MemOperand
operand
;
};
}
}
}
}
...
...
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