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SandHook
Commits
60f5426c
Commit
60f5426c
authored
May 19, 2019
by
swift_gan
Committed by
swift_gan
May 19, 2019
Browse files
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Plain Diff
[NativeHook]TWEAK CODE
parent
62dc8d9a
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Inline
Side-by-side
Showing
7 changed files
with
202 additions
and
5 deletions
+202
-5
arm32_base.h
nativehook/src/main/cpp/archs/arm/arm32/inst/arm32_base.h
+8
-0
inst_code_arm32.h
...ehook/src/main/cpp/archs/arm/arm32/inst/inst_code_arm32.h
+7
-1
inst_struct_t16.h
...ehook/src/main/cpp/archs/arm/arm32/inst/inst_struct_t16.h
+8
-1
inst_struct_t32.h
...ehook/src/main/cpp/archs/arm/arm32/inst/inst_struct_t32.h
+35
-0
inst_t32.cpp
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.cpp
+79
-1
inst_t32.h
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.h
+65
-1
instruction.h
nativehook/src/main/cpp/asm/instruction.h
+0
-1
No files found.
nativehook/src/main/cpp/archs/arm/arm32/inst/arm32_base.h
View file @
60f5426c
...
@@ -138,6 +138,14 @@ namespace SandHook {
...
@@ -138,6 +138,14 @@ namespace SandHook {
return
(
registers
.
GetList
()
>>
first
)
&
((
1
<<
count
)
-
1
);
return
(
registers
.
GetList
()
>>
first
)
&
((
1
<<
count
)
-
1
);
}
}
inline
bool
isThumbCode
(
Addr
codeAddr
)
{
return
(
codeAddr
&
0x1
)
==
0x1
;
}
inline
bool
isThumb32
(
InstT16
code
)
{
return
((
code
&
0xF000
)
==
0xF000
)
||
((
code
&
0xF800
)
==
0xE800
);
}
std
::
ostream
&
operator
<<
(
std
::
ostream
&
os
,
RegisterList
registers
);
std
::
ostream
&
operator
<<
(
std
::
ostream
&
os
,
RegisterList
registers
);
}
}
}
}
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_code_arm32.h
View file @
60f5426c
...
@@ -24,11 +24,17 @@ enum class InstCodeT16 {
...
@@ -24,11 +24,17 @@ enum class InstCodeT16 {
//rn = pc
//rn = pc
ADR
,
ADR
,
CMP_REG
,
CMP_REG
,
MOV_REG
MOV_IMM
,
MOV_REG
,
};
};
enum
class
InstCodeT32
{
enum
class
InstCodeT32
{
B32
,
B32
,
LDR_LIT
,
LDR_IMM
,
LDR_UIMM
,
LDRB_LIT
,
MOV_MOVT_IMM
};
};
#endif //SANDHOOK_INST_CODE_ARM32_H
#endif //SANDHOOK_INST_CODE_ARM32_H
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_struct_t16.h
View file @
60f5426c
...
@@ -102,12 +102,19 @@ DEFINE_STRUCT_T16(CMP_REG) {
...
@@ -102,12 +102,19 @@ DEFINE_STRUCT_T16(CMP_REG) {
DEFINE_OPCODE_T16
(
MOV_REG
,
0
b10
)
DEFINE_OPCODE_T16
(
MOV_REG
,
0
b10
)
DEFINE_STRUCT_T16
(
MOV_REG
)
{
DEFINE_STRUCT_T16
(
MOV_REG
)
{
InstT16
rd
:
3
;
InstT16
rd
:
T16_REG_WIDE
;
InstT16
rm
:
4
;
InstT16
rm
:
4
;
InstT16
D
:
1
;
InstT16
D
:
1
;
DEFINE_STRCUT_BASE_T16
(
6
,
2
)
DEFINE_STRCUT_BASE_T16
(
6
,
2
)
};
};
DEFINE_OPCODE_T16
(
MOV_IMM
,
0
b00100
)
DEFINE_STRUCT_T16
(
MOV_IMM
)
{
InstT16
imm8
:
8
;
InstT16
rd
:
T16_REG_WIDE
;
InstT16
opcode
:
5
;
};
#endif //SANDHOOK_NH_INST_STRUCT_T16_H
#endif //SANDHOOK_NH_INST_STRUCT_T16_H
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_struct_t32.h
View file @
60f5426c
...
@@ -13,6 +13,8 @@
...
@@ -13,6 +13,8 @@
#define DEFINE_OPCODE_T32(X, V) const U32 OPCODE_T32(X) = V;
#define DEFINE_OPCODE_T32(X, V) const U32 OPCODE_T32(X) = V;
#define DEFINE_STRUCT_T32(X) struct STRUCT_T32(X) : public Base
#define DEFINE_STRUCT_T32(X) struct STRUCT_T32(X) : public Base
#define T32_REG_WIDE 4
DEFINE_OPCODE_T32
(
B32
,
0
b11110
)
DEFINE_OPCODE_T32
(
B32
,
0
b11110
)
DEFINE_STRUCT_T32
(
B32
)
{
DEFINE_STRUCT_T32
(
B32
)
{
...
@@ -26,5 +28,38 @@ DEFINE_STRUCT_T32(B32) {
...
@@ -26,5 +28,38 @@ DEFINE_STRUCT_T32(B32) {
InstT32
opcode
:
5
;
InstT32
opcode
:
5
;
};
};
DEFINE_OPCODE_T32
(
LDR_LIT
,
0
b111100
)
DEFINE_STRUCT_T32
(
LDR_LIT
)
{
InstT32
imm12
:
12
;
InstT32
rt
:
T32_REG_WIDE
;
InstT32
op
:
7
;
InstT32
U
:
1
;
InstT32
S
:
1
;
InstT32
opcode
:
7
;
};
//ldr imm T3
DEFINE_OPCODE_T32
(
LDR_UIMM
,
0
b111110001101
)
DEFINE_STRUCT_T32
(
LDR_UIMM
)
{
InstT32
imm12
:
12
;
InstT32
rt
:
T32_REG_WIDE
;
InstT32
rn
:
T32_REG_WIDE
;
InstT32
opcode
:
12
;
};
DEFINE_OPCODE_T32
(
MOV_MOVT_IMM_1
,
0
b11110
)
DEFINE_OPCODE_T32
(
MOV_MOVT_IMM_2
,
0
b0
)
DEFINE_STRUCT_T32
(
MOV_MOVT_IMM
)
{
InstT32
imm8
:
8
;
InstT32
rd
:
4
;
InstT32
imm3
:
3
;
InstT32
opcode2
:
1
;
InstT32
imm4
:
4
;
InstT32
op
:
6
;
InstT32
i
:
1
;
InstT32
opcode1
:
5
;
};
#endif //SANDHOOK_NH_INST_STRUCT_T32_H
#endif //SANDHOOK_NH_INST_STRUCT_T32_H
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.cpp
View file @
60f5426c
...
@@ -24,16 +24,94 @@ T32_B32::T32_B32(T32_B32::OP op, T32_B32::X x, Label &label) : op(op), x(x) {
...
@@ -24,16 +24,94 @@ T32_B32::T32_B32(T32_B32::OP op, T32_B32::X x, Label &label) : op(op), x(x) {
}
}
Off
T32_B32
::
getImmPCOffset
()
{
Off
T32_B32
::
getImmPCOffset
()
{
//U16 immhi =
U32
S
=
get
()
->
S
;
U32
imm21
=
COMBINE
(
get
()
->
imm10
,
get
()
->
imm11
,
11
);
U32
i1
=
(
get
()
->
J1
^
S
)
?
0
:
1
;
U32
i2
=
(
get
()
->
J2
^
S
)
?
0
:
1
;
U32
i1i2
=
COMBINE
(
i1
,
i2
,
1
);
U32
Si1i2
=
COMBINE
(
S
,
i1i2
,
2
);
//BLX
if
(
op
==
BL
&&
x
==
thumb
)
{
INST_ASSERT
((
imm21
&
0x1
)
==
0x1
);
}
return
signExtend32
(
25
,
COMBINE
(
Si1i2
,
imm21
,
21
)
<<
0
);
}
}
void
T32_B32
::
decode
(
T32_STRUCT_B32
*
inst
)
{
void
T32_B32
::
decode
(
T32_STRUCT_B32
*
inst
)
{
DECODE_OP
;
DECODE_OP
;
x
=
X
(
inst
->
X
);
x
=
X
(
inst
->
X
);
offset
=
getImmPCOffset
();
}
}
void
T32_B32
::
assembler
()
{
void
T32_B32
::
assembler
()
{
SET_OPCODE
(
B32
);
SET_OPCODE
(
B32
);
ENCODE_OP
;
ENCODE_OP
;
get
()
->
X
=
x
;
get
()
->
X
=
x
;
U32
imm24
=
TruncateToUint25
(
offset
)
>>
0
;
get
()
->
imm11
=
BITS
(
imm24
,
0
,
10
);
get
()
->
imm10
=
BITS
(
imm24
,
11
,
20
);
get
()
->
S
=
BIT
(
imm24
,
23
);
U32
i1
=
BIT
(
imm24
,
22
);
U32
i2
=
BIT
(
imm24
,
21
);
if
(
i1
==
1
)
{
get
()
->
J1
=
get
()
->
S
;
}
else
{
get
()
->
J1
=
~
get
()
->
S
;
}
if
(
i2
==
1
)
{
get
()
->
J2
=
get
()
->
S
;
}
else
{
get
()
->
J2
=
~
get
()
->
S
;
}
}
T32_LDR_UIMM
::
T32_LDR_UIMM
(
T32_STRUCT_LDR_UIMM
*
inst
)
:
InstructionT32
(
inst
)
{}
T32_LDR_UIMM
::
T32_LDR_UIMM
(
RegisterA32
&
rt
,
RegisterA32
&
rn
,
U32
offset
)
:
rt
(
&
rt
),
rn
(
&
rn
),
offset
(
offset
)
{}
void
T32_LDR_UIMM
::
decode
(
T32_STRUCT_LDR_UIMM
*
inst
)
{
DECODE_RN
(
Reg
);
DECODE_RT
(
Reg
);
INST_ASSERT
(
rn
==
&
PC
);
offset
=
inst
->
imm12
;
}
void
T32_LDR_UIMM
::
assembler
()
{
SET_OPCODE
(
LDR_UIMM
);
ENCODE_RN
;
ENCODE_RT
;
INST_ASSERT
(
rn
==
&
PC
);
get
()
->
imm12
=
offset
;
}
T32_LDR_LIT
::
T32_LDR_LIT
()
{}
T32_LDR_LIT
::
T32_LDR_LIT
(
T32_STRUCT_LDR_LIT
*
inst
)
:
T32_INST_PC_REL
(
inst
)
{}
T32_LDR_LIT
::
T32_LDR_LIT
(
RegisterA32
&
rt
,
Off
offset
)
:
rt
(
&
rt
),
offset
(
offset
)
{}
Off
T32_LDR_LIT
::
getImmPCOffset
()
{
return
get
()
->
U
==
add
?
get
()
->
imm12
:
-
get
()
->
imm12
;
}
void
T32_LDR_LIT
::
decode
(
T32_STRUCT_LDR_LIT
*
inst
)
{
DECODE_OP
;
DECODE_RT
(
Reg
);
offset
=
getImmPCOffset
();
}
void
T32_LDR_LIT
::
assembler
()
{
SET_OPCODE
(
LDR_LIT
);
ENCODE_OP
;
ENCODE_RT
;
if
(
offset
>=
0
)
{
get
()
->
U
=
add
;
get
()
->
imm12
=
static_cast
<
InstT32
>
(
offset
);
}
else
{
get
()
->
U
=
cmp
;
get
()
->
imm12
=
static_cast
<
InstT32
>
(
-
offset
);
}
}
}
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.h
View file @
60f5426c
...
@@ -35,7 +35,7 @@ return COND; \
...
@@ -35,7 +35,7 @@ return COND; \
#define DEFINE_INST_CODE(X) \
#define DEFINE_INST_CODE(X) \
inline U32 instCode() override { \
inline U32 instCode() override { \
return
InstCodeT32::X
; \
return
ENUM_VALUE(InstCodeT32, InstCodeT32::X)
; \
}
}
using
namespace
SandHook
::
RegistersA32
;
using
namespace
SandHook
::
RegistersA32
;
...
@@ -121,6 +121,10 @@ namespace SandHook {
...
@@ -121,6 +121,10 @@ namespace SandHook {
T32_B32
(
OP
op
,
X
x
,
Label
&
label
);
T32_B32
(
OP
op
,
X
x
,
Label
&
label
);
DEFINE_INST_CODE
(
B32
)
DEFINE_IS
(
B32
)
Off
getImmPCOffset
()
override
;
Off
getImmPCOffset
()
override
;
void
decode
(
T32_STRUCT_B32
*
inst
)
override
;
void
decode
(
T32_STRUCT_B32
*
inst
)
override
;
...
@@ -133,6 +137,66 @@ namespace SandHook {
...
@@ -133,6 +137,66 @@ namespace SandHook {
Off
offset
;
Off
offset
;
};
};
class
INST_T32
(
LDR_UIMM
)
:
public
InstructionT32
<
STRUCT_T32
(
LDR_UIMM
)
>
{
public
:
T32_LDR_UIMM
(
T32_STRUCT_LDR_UIMM
*
inst
);
T32_LDR_UIMM
(
RegisterA32
&
rt
,
RegisterA32
&
rn
,
U32
offset
);
DEFINE_INST_CODE
(
LDR_UIMM
)
DEFINE_IS
(
LDR_UIMM
)
void
decode
(
T32_STRUCT_LDR_UIMM
*
inst
)
override
;
void
assembler
()
override
;
public
:
RegisterA32
*
rt
;
RegisterA32
*
rn
;
U32
offset
;
};
class
INST_T32
(
LDR_LIT
)
:
public
T32_INST_PC_REL
<
STRUCT_T32
(
LDR_LIT
)
>
{
public
:
enum
OP
{
LDR
=
0
b1011111
,
LDRB
=
0
b0011111
,
LDRH
=
0
b0111111
};
enum
S
{
cmp
=
0
,
add
=
1
};
T32_LDR_LIT
();
T32_LDR_LIT
(
T32_STRUCT_LDR_LIT
*
inst
);
T32_LDR_LIT
(
RegisterA32
&
rt
,
Off
offset
);
DEFINE_IS
(
LDR_LIT
)
DEFINE_INST_CODE
(
LDR_LIT
)
Off
getImmPCOffset
()
override
;
void
decode
(
T32_STRUCT_LDR_LIT
*
inst
)
override
;
void
assembler
()
override
;
public
:
OP
op
;
RegisterA32
*
rt
;
Off
offset
;
};
}
}
}
}
...
...
nativehook/src/main/cpp/asm/instruction.h
View file @
60f5426c
...
@@ -31,7 +31,6 @@ DCHECK(X,V, valid = false;)
...
@@ -31,7 +31,6 @@ DCHECK(X,V, valid = false;)
#define INST_ASSERT(COND) \
#define INST_ASSERT(COND) \
if (COND) { \
if (COND) { \
valid = false; \
valid = false; \
return; \
}
}
namespace
SandHook
{
namespace
SandHook
{
...
...
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