Commit 612980be authored by swift_gan's avatar swift_gan Committed by swift_gan

[Reconstitution]tweak typo

parent c2a9a03f
...@@ -42,7 +42,7 @@ ...@@ -42,7 +42,7 @@
//} //}
// //
// //
//void A64_STR_IMM::Assembler() { //void A64_STR_IMM::Assemble() {
// INST_DCHECK(condition, Condition::nv) // INST_DCHECK(condition, Condition::nv)
// //
//} //}
\ No newline at end of file
...@@ -25,7 +25,7 @@ namespace SandHook { ...@@ -25,7 +25,7 @@ namespace SandHook {
// //
// void DisAssembler(STRUCT_A64(STR_IMM) *inst) override; // void DisAssembler(STRUCT_A64(STR_IMM) *inst) override;
// //
// void Assembler() override; // void Assemble() override;
// //
// AddrMode getAddrMode() { // AddrMode getAddrMode() {
// return operand.addr_mode_; // return operand.addr_mode_;
......
...@@ -35,11 +35,11 @@ Off T16_B::GetImmPCOffset() { ...@@ -35,11 +35,11 @@ Off T16_B::GetImmPCOffset() {
return DECODE_OFFSET(11, 1); return DECODE_OFFSET(11, 1);
} }
void T16_B::Disassembler() { void T16_B::Disassemble() {
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void T16_B::Assembler() { void T16_B::Assemble() {
SET_OPCODE(B); SET_OPCODE(B);
DECODE_OFFSET(11, 1); DECODE_OFFSET(11, 1);
} }
...@@ -62,12 +62,12 @@ T16_B_COND::T16_B_COND(Condition condition, Label *label) { ...@@ -62,12 +62,12 @@ T16_B_COND::T16_B_COND(Condition condition, Label *label) {
BindLabel(label); BindLabel(label);
} }
void T16_B_COND::Disassembler() { void T16_B_COND::Disassemble() {
DECODE_COND; DECODE_COND;
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void T16_B_COND::Assembler() { void T16_B_COND::Assemble() {
SET_OPCODE(B_COND); SET_OPCODE(B_COND);
ENCODE_COND; ENCODE_COND;
ENCODE_OFFSET(8, 1); ENCODE_OFFSET(8, 1);
...@@ -89,12 +89,12 @@ T16_BX_BLX::T16_BX_BLX(void *inst) : T16_INST_PC_REL(inst) {} ...@@ -89,12 +89,12 @@ T16_BX_BLX::T16_BX_BLX(void *inst) : T16_INST_PC_REL(inst) {}
T16_BX_BLX::T16_BX_BLX(T16_BX_BLX::OP op, RegisterA32 &rm) : op(op), rm(&rm) {} T16_BX_BLX::T16_BX_BLX(T16_BX_BLX::OP op, RegisterA32 &rm) : op(op), rm(&rm) {}
void T16_BX_BLX::Disassembler() { void T16_BX_BLX::Disassemble() {
DECODE_OP; DECODE_OP;
DECODE_RM(Reg); DECODE_RM(Reg);
} }
void T16_BX_BLX::Assembler() { void T16_BX_BLX::Assemble() {
SET_OPCODE_MULTI(BX_BLX, 1); SET_OPCODE_MULTI(BX_BLX, 1);
SET_OPCODE_MULTI(BX_BLX, 2); SET_OPCODE_MULTI(BX_BLX, 2);
ENCODE_OP; ENCODE_OP;
...@@ -116,13 +116,13 @@ Off T16_CBZ_CBNZ::GetImmPCOffset() { ...@@ -116,13 +116,13 @@ Off T16_CBZ_CBNZ::GetImmPCOffset() {
return COMBINE(Get()->i, Get()->imm5, 5) << 2; return COMBINE(Get()->i, Get()->imm5, 5) << 2;
} }
void T16_CBZ_CBNZ::Disassembler() { void T16_CBZ_CBNZ::Disassemble() {
offset = GetImmPCOffset(); offset = GetImmPCOffset();
DECODE_RN(Reg); DECODE_RN(Reg);
DECODE_OP; DECODE_OP;
} }
void T16_CBZ_CBNZ::Assembler() { void T16_CBZ_CBNZ::Assemble() {
SET_OPCODE_MULTI(CBZ_CBNZ, 1); SET_OPCODE_MULTI(CBZ_CBNZ, 1);
SET_OPCODE_MULTI(CBZ_CBNZ, 2); SET_OPCODE_MULTI(CBZ_CBNZ, 2);
SET_OPCODE_MULTI(CBZ_CBNZ, 3); SET_OPCODE_MULTI(CBZ_CBNZ, 3);
...@@ -155,12 +155,12 @@ void T16_LDR_LIT::OnOffsetApply(Off offset) { ...@@ -155,12 +155,12 @@ void T16_LDR_LIT::OnOffsetApply(Off offset) {
ENCODE_OFFSET(8, 2); ENCODE_OFFSET(8, 2);
} }
void T16_LDR_LIT::Disassembler() { void T16_LDR_LIT::Disassemble() {
DECODE_RT(Reg); DECODE_RT(Reg);
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void T16_LDR_LIT::Assembler() { void T16_LDR_LIT::Assemble() {
SET_OPCODE(LDR_LIT); SET_OPCODE(LDR_LIT);
ENCODE_RT; ENCODE_RT;
ENCODE_OFFSET(8, 2); ENCODE_OFFSET(8, 2);
...@@ -174,12 +174,12 @@ T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(void *inst) : InstructionT16(inst) {} ...@@ -174,12 +174,12 @@ T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(void *inst) : InstructionT16(inst) {}
T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(RegisterA32 *rdn, U8 imm8) : rdn(rdn), imm8(imm8) {} T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(RegisterA32 *rdn, U8 imm8) : rdn(rdn), imm8(imm8) {}
void T16_ADD_IMM_RDN::Disassembler() { void T16_ADD_IMM_RDN::Disassemble() {
rdn = Reg(Get()->rdn); rdn = Reg(Get()->rdn);
imm8 = Get()->imm8; imm8 = Get()->imm8;
} }
void T16_ADD_IMM_RDN::Assembler() { void T16_ADD_IMM_RDN::Assemble() {
SET_OPCODE(ADD_IMM_RDN); SET_OPCODE(ADD_IMM_RDN);
Get()->imm8 = imm8; Get()->imm8 = imm8;
Get()->rdn = rdn->Code(); Get()->rdn = rdn->Code();
...@@ -211,13 +211,13 @@ void T16_ADR::OnOffsetApply(Off offset) { ...@@ -211,13 +211,13 @@ void T16_ADR::OnOffsetApply(Off offset) {
Get()->imm8 = (U32)offset >> 2; Get()->imm8 = (U32)offset >> 2;
} }
void T16_ADR::Disassembler() { void T16_ADR::Disassemble() {
offset = GetImmPCOffset(); offset = GetImmPCOffset();
DECODE_RD(Reg); DECODE_RD(Reg);
} }
void T16_ADR::Assembler() { void T16_ADR::Assemble() {
SET_OPCODE(ADR); SET_OPCODE(ADR);
ENCODE_RD; ENCODE_RD;
Get()->imm8 = (U32)offset >> 2; Get()->imm8 = (U32)offset >> 2;
...@@ -228,12 +228,12 @@ T16_CMP_REG::T16_CMP_REG(void *inst) : InstructionT16(inst) {} ...@@ -228,12 +228,12 @@ T16_CMP_REG::T16_CMP_REG(void *inst) : InstructionT16(inst) {}
T16_CMP_REG::T16_CMP_REG(RegisterA32 &rm, RegisterA32 &rn) : rm(&rm), rn(&rn) {} T16_CMP_REG::T16_CMP_REG(RegisterA32 &rm, RegisterA32 &rn) : rm(&rm), rn(&rn) {}
void T16_CMP_REG::Disassembler() { void T16_CMP_REG::Disassemble() {
DECODE_RM(Reg); DECODE_RM(Reg);
DECODE_RN(Reg); DECODE_RN(Reg);
} }
void T16_CMP_REG::Assembler() { void T16_CMP_REG::Assemble() {
SET_BASE_OPCODE(DATA_PROC); SET_BASE_OPCODE(DATA_PROC);
SET_OPCODE(CMP_REG); SET_OPCODE(CMP_REG);
ENCODE_RM; ENCODE_RM;
...@@ -246,12 +246,12 @@ T16_MOV_REG::T16_MOV_REG(void *inst) : InstructionT16(inst) {} ...@@ -246,12 +246,12 @@ T16_MOV_REG::T16_MOV_REG(void *inst) : InstructionT16(inst) {}
T16_MOV_REG::T16_MOV_REG(RegisterA32 &rd, RegisterA32 &rm) : rm(&rm), rd(&rd) {} T16_MOV_REG::T16_MOV_REG(RegisterA32 &rd, RegisterA32 &rm) : rm(&rm), rd(&rd) {}
void T16_MOV_REG::Disassembler() { void T16_MOV_REG::Disassemble() {
DECODE_RM(Reg); DECODE_RM(Reg);
rd = Reg(static_cast<U8>(COMBINE(Get()->D, Get()->rd, 3))); rd = Reg(static_cast<U8>(COMBINE(Get()->D, Get()->rd, 3)));
} }
void T16_MOV_REG::Assembler() { void T16_MOV_REG::Assemble() {
SET_BASE_OPCODE(DATA_PROC); SET_BASE_OPCODE(DATA_PROC);
SET_OPCODE(MOV_REG); SET_OPCODE(MOV_REG);
ENCODE_RM; ENCODE_RM;
...@@ -271,13 +271,13 @@ T16_ADD_REG::T16_ADD_REG(void *inst) : InstructionT16(inst) {} ...@@ -271,13 +271,13 @@ T16_ADD_REG::T16_ADD_REG(void *inst) : InstructionT16(inst) {}
T16_ADD_REG::T16_ADD_REG(RegisterA32 *rd, RegisterA32 *rn, RegisterA32 *rm) : rd(rd), rn(rn), T16_ADD_REG::T16_ADD_REG(RegisterA32 *rd, RegisterA32 *rn, RegisterA32 *rm) : rd(rd), rn(rn),
rm(rm) {} rm(rm) {}
void T16_ADD_REG::Disassembler() { void T16_ADD_REG::Disassemble() {
DECODE_RD(Reg); DECODE_RD(Reg);
DECODE_RN(Reg); DECODE_RN(Reg);
DECODE_RM(Reg); DECODE_RM(Reg);
} }
void T16_ADD_REG::Assembler() { void T16_ADD_REG::Assemble() {
SET_OPCODE(ADD_REG); SET_OPCODE(ADD_REG);
INST_ASSERT(rd->Code() > 7); INST_ASSERT(rd->Code() > 7);
INST_ASSERT(rn->Code() > 7); INST_ASSERT(rn->Code() > 7);
...@@ -293,12 +293,12 @@ T16_CMP_REG_EXT::T16_CMP_REG_EXT(void *inst) : InstructionT16(inst) {} ...@@ -293,12 +293,12 @@ T16_CMP_REG_EXT::T16_CMP_REG_EXT(void *inst) : InstructionT16(inst) {}
T16_CMP_REG_EXT::T16_CMP_REG_EXT(RegisterA32 &rn, RegisterA32 &rm) : rn(&rn), rm(&rm) {} T16_CMP_REG_EXT::T16_CMP_REG_EXT(RegisterA32 &rn, RegisterA32 &rm) : rn(&rn), rm(&rm) {}
void T16_CMP_REG_EXT::Disassembler() { void T16_CMP_REG_EXT::Disassemble() {
rn = Reg(COMBINE(Get()->N, Get()->rn, 3)); rn = Reg(COMBINE(Get()->N, Get()->rn, 3));
DECODE_RM(Reg); DECODE_RM(Reg);
} }
void T16_CMP_REG_EXT::Assembler() { void T16_CMP_REG_EXT::Assemble() {
SET_OPCODE(CMP_REG_EXT); SET_OPCODE(CMP_REG_EXT);
ENCODE_RM; ENCODE_RM;
Get()->rn = BITS(rn->Code(), 0, 2); Get()->rn = BITS(rn->Code(), 0, 2);
...@@ -311,11 +311,11 @@ T16_POP::T16_POP(void *inst) : InstructionT16(inst) {} ...@@ -311,11 +311,11 @@ T16_POP::T16_POP(void *inst) : InstructionT16(inst) {}
T16_POP::T16_POP(const RegisterList &registerList) : registerList(registerList) {} T16_POP::T16_POP(const RegisterList &registerList) : registerList(registerList) {}
void T16_POP::Disassembler() { void T16_POP::Disassemble() {
registerList.SetList(COMBINE(Get()->P << 7, Get()->regs, 8)); registerList.SetList(COMBINE(Get()->P << 7, Get()->regs, 8));
} }
void T16_POP::Assembler() { void T16_POP::Assemble() {
SET_OPCODE(POP); SET_OPCODE(POP);
U16 regs = registerList.GetList(); U16 regs = registerList.GetList();
Get()->regs = BITS(regs, 0, 7); Get()->regs = BITS(regs, 0, 7);
...@@ -328,11 +328,11 @@ T16_PUSH::T16_PUSH(void *inst) : InstructionT16(inst) {} ...@@ -328,11 +328,11 @@ T16_PUSH::T16_PUSH(void *inst) : InstructionT16(inst) {}
T16_PUSH::T16_PUSH(const RegisterList &registerList) : registerList(registerList) {} T16_PUSH::T16_PUSH(const RegisterList &registerList) : registerList(registerList) {}
void T16_PUSH::Disassembler() { void T16_PUSH::Disassemble() {
registerList.SetList(COMBINE(Get()->M << 6, Get()->regs, 8)); registerList.SetList(COMBINE(Get()->M << 6, Get()->regs, 8));
} }
void T16_PUSH::Assembler() { void T16_PUSH::Assemble() {
SET_OPCODE(PUSH); SET_OPCODE(PUSH);
U16 regs = registerList.GetList(); U16 regs = registerList.GetList();
Get()->regs = BITS(regs, 0, 7); Get()->regs = BITS(regs, 0, 7);
...@@ -349,12 +349,12 @@ bool T16_ADD_REG_RDN::PcRelate() { ...@@ -349,12 +349,12 @@ bool T16_ADD_REG_RDN::PcRelate() {
return *rm == PC; return *rm == PC;
} }
void T16_ADD_REG_RDN::Disassembler() { void T16_ADD_REG_RDN::Disassemble() {
DECODE_RM(Reg); DECODE_RM(Reg);
rdn = Reg(Get()->rdn); rdn = Reg(Get()->rdn);
} }
void T16_ADD_REG_RDN::Assembler() { void T16_ADD_REG_RDN::Assemble() {
SET_OPCODE(ADD_REG_RDN); SET_OPCODE(ADD_REG_RDN);
ENCODE_RM; ENCODE_RM;
Get()->rdn = rdn->Code(); Get()->rdn = rdn->Code();
......
...@@ -128,9 +128,9 @@ namespace SandHook { ...@@ -128,9 +128,9 @@ namespace SandHook {
Off GetImmPCOffset() override; Off GetImmPCOffset() override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
Off offset; Off offset;
...@@ -152,9 +152,9 @@ namespace SandHook { ...@@ -152,9 +152,9 @@ namespace SandHook {
void OnOffsetApply(Off offset) override; void OnOffsetApply(Off offset) override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
Condition condition; Condition condition;
...@@ -176,9 +176,9 @@ namespace SandHook { ...@@ -176,9 +176,9 @@ namespace SandHook {
DEFINE_IS_EXT(BX_BLX, TEST_INST_OPCODE(BX_BLX, 1) && TEST_INST_OPCODE(BX_BLX, 2)) DEFINE_IS_EXT(BX_BLX, TEST_INST_OPCODE(BX_BLX, 1) && TEST_INST_OPCODE(BX_BLX, 2))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -207,9 +207,9 @@ namespace SandHook { ...@@ -207,9 +207,9 @@ namespace SandHook {
Off GetImmPCOffset() override; Off GetImmPCOffset() override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -233,9 +233,9 @@ namespace SandHook { ...@@ -233,9 +233,9 @@ namespace SandHook {
void OnOffsetApply(Off offset) override; void OnOffsetApply(Off offset) override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
Off offset; Off offset;
...@@ -251,9 +251,9 @@ namespace SandHook { ...@@ -251,9 +251,9 @@ namespace SandHook {
DEFINE_IS(ADD_IMM_RDN) DEFINE_IS(ADD_IMM_RDN)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterA32 *rdn; RegisterA32 *rdn;
...@@ -277,9 +277,9 @@ namespace SandHook { ...@@ -277,9 +277,9 @@ namespace SandHook {
void OnOffsetApply(Off offset) override; void OnOffsetApply(Off offset) override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterA32 *rd; RegisterA32 *rd;
...@@ -298,9 +298,9 @@ namespace SandHook { ...@@ -298,9 +298,9 @@ namespace SandHook {
DEFINE_IS_EXT(CMP_REG, TEST_INST_FIELD(opcode_base, OPCODE_T16(DATA_PROC)) && DEFINE_IS_EXT(CMP_REG, TEST_INST_FIELD(opcode_base, OPCODE_T16(DATA_PROC)) &&
TEST_INST_FIELD(opcode, OPCODE_T16(CMP_REG))) TEST_INST_FIELD(opcode, OPCODE_T16(CMP_REG)))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterA32 *rm; RegisterA32 *rm;
...@@ -318,9 +318,9 @@ namespace SandHook { ...@@ -318,9 +318,9 @@ namespace SandHook {
DEFINE_IS_EXT(MOV_REG, TEST_INST_FIELD(opcode_base, OPCODE_T16(DATA_PROC)) && DEFINE_IS_EXT(MOV_REG, TEST_INST_FIELD(opcode_base, OPCODE_T16(DATA_PROC)) &&
TEST_INST_FIELD(opcode, OPCODE_T16(MOV_REG))) TEST_INST_FIELD(opcode, OPCODE_T16(MOV_REG)))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
bool PcRelate() override; bool PcRelate() override;
...@@ -339,9 +339,9 @@ namespace SandHook { ...@@ -339,9 +339,9 @@ namespace SandHook {
DEFINE_IS(ADD_REG) DEFINE_IS(ADD_REG)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterA32 *rd; RegisterA32 *rd;
...@@ -359,9 +359,9 @@ namespace SandHook { ...@@ -359,9 +359,9 @@ namespace SandHook {
DEFINE_IS(CMP_REG_EXT) DEFINE_IS(CMP_REG_EXT)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
...@@ -378,9 +378,9 @@ namespace SandHook { ...@@ -378,9 +378,9 @@ namespace SandHook {
DEFINE_IS(POP) DEFINE_IS(POP)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterList registerList; RegisterList registerList;
...@@ -396,9 +396,9 @@ namespace SandHook { ...@@ -396,9 +396,9 @@ namespace SandHook {
DEFINE_IS(PUSH) DEFINE_IS(PUSH)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterList registerList; RegisterList registerList;
...@@ -417,9 +417,9 @@ namespace SandHook { ...@@ -417,9 +417,9 @@ namespace SandHook {
bool PcRelate() override; bool PcRelate() override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterA32* rdn; RegisterA32* rdn;
......
...@@ -45,13 +45,13 @@ Off T32_B32::GetImmPCOffset() { ...@@ -45,13 +45,13 @@ Off T32_B32::GetImmPCOffset() {
return SignExtend32(25, COMBINE(Si1i2, imm21, 21) << 1); return SignExtend32(25, COMBINE(Si1i2, imm21, 21) << 1);
} }
void T32_B32::Disassembler() { void T32_B32::Disassemble() {
DECODE_OP; DECODE_OP;
x = X(Get()->X); x = X(Get()->X);
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void T32_B32::Assembler() { void T32_B32::Assemble() {
SET_OPCODE(B32); SET_OPCODE(B32);
ENCODE_OP; ENCODE_OP;
Get()->X = x; Get()->X = x;
...@@ -91,14 +91,14 @@ T32_LDR_UIMM::T32_LDR_UIMM(void *inst) : InstructionT32(inst) {} ...@@ -91,14 +91,14 @@ T32_LDR_UIMM::T32_LDR_UIMM(void *inst) : InstructionT32(inst) {}
T32_LDR_UIMM::T32_LDR_UIMM(RegisterA32 &rt, RegisterA32 &rn, U32 offset) : rt(&rt), rn(&rn), T32_LDR_UIMM::T32_LDR_UIMM(RegisterA32 &rt, RegisterA32 &rn, U32 offset) : rt(&rt), rn(&rn),
offset(offset) {} offset(offset) {}
void T32_LDR_UIMM::Disassembler() { void T32_LDR_UIMM::Disassemble() {
DECODE_RN(Reg); DECODE_RN(Reg);
DECODE_RT(Reg); DECODE_RT(Reg);
INST_ASSERT(rn == &PC); INST_ASSERT(rn == &PC);
offset = Get()->imm12; offset = Get()->imm12;
} }
void T32_LDR_UIMM::Assembler() { void T32_LDR_UIMM::Assemble() {
SET_OPCODE(LDR_UIMM); SET_OPCODE(LDR_UIMM);
ENCODE_RN; ENCODE_RN;
ENCODE_RT; ENCODE_RT;
...@@ -131,14 +131,14 @@ void T32_LDR_LIT::OnOffsetApply(Off offset) { ...@@ -131,14 +131,14 @@ void T32_LDR_LIT::OnOffsetApply(Off offset) {
} }
} }
void T32_LDR_LIT::Disassembler() { void T32_LDR_LIT::Disassemble() {
DECODE_OP; DECODE_OP;
DECODE_RT(Reg); DECODE_RT(Reg);
s = S(Get()->S); s = S(Get()->S);
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void T32_LDR_LIT::Assembler() { void T32_LDR_LIT::Assemble() {
SET_OPCODE(LDR_LIT); SET_OPCODE(LDR_LIT);
ENCODE_OP; ENCODE_OP;
ENCODE_RT; ENCODE_RT;
...@@ -161,7 +161,7 @@ T32_MOV_MOVT_IMM::T32_MOV_MOVT_IMM(T32_MOV_MOVT_IMM::OP op, RegisterA32 &rd, U16 ...@@ -161,7 +161,7 @@ T32_MOV_MOVT_IMM::T32_MOV_MOVT_IMM(T32_MOV_MOVT_IMM::OP op, RegisterA32 &rd, U16
rd(&rd), rd(&rd),
imm16(imm16) {} imm16(imm16) {}
void T32_MOV_MOVT_IMM::Disassembler() { void T32_MOV_MOVT_IMM::Disassemble() {
DECODE_OP; DECODE_OP;
DECODE_RD(Reg); DECODE_RD(Reg);
U16 imm4i = COMBINE(Get()->imm4, Get()->i, 1); U16 imm4i = COMBINE(Get()->imm4, Get()->i, 1);
...@@ -169,7 +169,7 @@ void T32_MOV_MOVT_IMM::Disassembler() { ...@@ -169,7 +169,7 @@ void T32_MOV_MOVT_IMM::Disassembler() {
imm16 = COMBINE(imm4i, imm38, 11); imm16 = COMBINE(imm4i, imm38, 11);
} }
void T32_MOV_MOVT_IMM::Assembler() { void T32_MOV_MOVT_IMM::Assemble() {
SET_OPCODE_MULTI(MOV_MOVT_IMM, 1); SET_OPCODE_MULTI(MOV_MOVT_IMM, 1);
SET_OPCODE_MULTI(MOV_MOVT_IMM, 2); SET_OPCODE_MULTI(MOV_MOVT_IMM, 2);
ENCODE_OP; ENCODE_OP;
...@@ -188,7 +188,7 @@ T32_LDR_IMM::T32_LDR_IMM(T32_LDR_IMM::OP op, RegisterA32 &rt, const MemOperand & ...@@ -188,7 +188,7 @@ T32_LDR_IMM::T32_LDR_IMM(T32_LDR_IMM::OP op, RegisterA32 &rt, const MemOperand &
rt(&rt), rt(&rt),
operand(operand) {} operand(operand) {}
void T32_LDR_IMM::Disassembler() { void T32_LDR_IMM::Disassemble() {
DECODE_OP; DECODE_OP;
DECODE_RT(Reg); DECODE_RT(Reg);
operand.rn = Reg(static_cast<U8>(Get()->rn)); operand.rn = Reg(static_cast<U8>(Get()->rn));
...@@ -204,7 +204,7 @@ void T32_LDR_IMM::Disassembler() { ...@@ -204,7 +204,7 @@ void T32_LDR_IMM::Disassembler() {
operand.offset = Get()->U == 0 ? -Get()->imm8 : Get()->imm8; operand.offset = Get()->U == 0 ? -Get()->imm8 : Get()->imm8;
} }
void T32_LDR_IMM::Assembler() { void T32_LDR_IMM::Assemble() {
SET_OPCODE_MULTI(LDR_IMM, 1); SET_OPCODE_MULTI(LDR_IMM, 1);
SET_OPCODE_MULTI(LDR_IMM, 2); SET_OPCODE_MULTI(LDR_IMM, 2);
ENCODE_OP; ENCODE_OP;
......
...@@ -140,9 +140,9 @@ namespace SandHook { ...@@ -140,9 +140,9 @@ namespace SandHook {
Off GetImmPCOffset() override; Off GetImmPCOffset() override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -159,9 +159,9 @@ namespace SandHook { ...@@ -159,9 +159,9 @@ namespace SandHook {
DEFINE_IS(LDR_UIMM) DEFINE_IS(LDR_UIMM)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterA32* rt; RegisterA32* rt;
...@@ -201,9 +201,9 @@ namespace SandHook { ...@@ -201,9 +201,9 @@ namespace SandHook {
void OnOffsetApply(Off offset) override; void OnOffsetApply(Off offset) override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -227,9 +227,9 @@ namespace SandHook { ...@@ -227,9 +227,9 @@ namespace SandHook {
DEFINE_IS_EXT(MOV_MOVT_IMM, TEST_INST_OPCODE(MOV_MOVT_IMM, 1) && TEST_INST_OPCODE(MOV_MOVT_IMM, 2) && (TEST_INST_FIELD(op, MOV) || TEST_INST_FIELD(op, MOVT))) DEFINE_IS_EXT(MOV_MOVT_IMM, TEST_INST_OPCODE(MOV_MOVT_IMM, 1) && TEST_INST_OPCODE(MOV_MOVT_IMM, 2) && (TEST_INST_FIELD(op, MOV) || TEST_INST_FIELD(op, MOVT)))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -255,9 +255,9 @@ namespace SandHook { ...@@ -255,9 +255,9 @@ namespace SandHook {
DEFINE_IS_EXT(LDR_IMM, TEST_INST_OPCODE(LDR_IMM, 1) && TEST_INST_OPCODE(LDR_IMM, 2)) DEFINE_IS_EXT(LDR_IMM, TEST_INST_OPCODE(LDR_IMM, 1) && TEST_INST_OPCODE(LDR_IMM, 2))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
......
...@@ -50,7 +50,7 @@ void Arm64Decoder::Disassembler(void *codeStart, Addr codeLen, InstVisitor &visi ...@@ -50,7 +50,7 @@ void Arm64Decoder::Disassembler(void *codeStart, Addr codeLen, InstVisitor &visi
if (unit == nullptr) { if (unit == nullptr) {
unit = reinterpret_cast<BaseUnit*>(new INST_A64(UNKNOW)(pc)); unit = reinterpret_cast<BaseUnit*>(new INST_A64(UNKNOW)(pc));
} }
reinterpret_cast<BaseInst*>(unit)->Disassembler(); reinterpret_cast<BaseInst*>(unit)->Disassemble();
if (!visitor.Visit(unit, pc)) { if (!visitor.Visit(unit, pc)) {
break; break;
} }
......
...@@ -62,11 +62,11 @@ Addr A64_ADR_ADRP::GetImmPCOffsetTarget() { ...@@ -62,11 +62,11 @@ Addr A64_ADR_ADRP::GetImmPCOffsetTarget() {
return offset + reinterpret_cast<Addr>(base); return offset + reinterpret_cast<Addr>(base);
} }
void A64_ADR_ADRP::Assembler() { void A64_ADR_ADRP::Assemble() {
SET_OPCODE(ADR_ADRP); SET_OPCODE(ADR_ADRP);
} }
void A64_ADR_ADRP::Disassembler() { void A64_ADR_ADRP::Disassemble() {
offset = GetImmPCOffset(); offset = GetImmPCOffset();
DECODE_RD(XReg); DECODE_RD(XReg);
DECODE_OP; DECODE_OP;
...@@ -79,7 +79,7 @@ A64_MOV_WIDE::A64_MOV_WIDE(void* inst) : InstructionA64(inst) {} ...@@ -79,7 +79,7 @@ A64_MOV_WIDE::A64_MOV_WIDE(void* inst) : InstructionA64(inst) {}
A64_MOV_WIDE::A64_MOV_WIDE(A64_MOV_WIDE::OP op,RegisterA64* rd, U16 imme, U8 shift) A64_MOV_WIDE::A64_MOV_WIDE(A64_MOV_WIDE::OP op,RegisterA64* rd, U16 imme, U8 shift)
: shift(shift), op(op), imme(imme), rd(rd) {} : shift(shift), op(op), imme(imme), rd(rd) {}
void A64_MOV_WIDE::Assembler() { void A64_MOV_WIDE::Assemble() {
SET_OPCODE(MOV_WIDE); SET_OPCODE(MOV_WIDE);
Get()->imm16 = imme; Get()->imm16 = imme;
Get()->hw = static_cast<InstA64>(shift / 16); Get()->hw = static_cast<InstA64>(shift / 16);
...@@ -88,7 +88,7 @@ void A64_MOV_WIDE::Assembler() { ...@@ -88,7 +88,7 @@ void A64_MOV_WIDE::Assembler() {
ENCODE_RD; ENCODE_RD;
} }
void A64_MOV_WIDE::Disassembler() { void A64_MOV_WIDE::Disassemble() {
imme = static_cast<U16>(Get()->imm16); imme = static_cast<U16>(Get()->imm16);
shift = static_cast<U8>(Get()->hw * 16); shift = static_cast<U8>(Get()->hw * 16);
op = OP(Get()->op); op = OP(Get()->op);
...@@ -122,12 +122,12 @@ void A64_B_BL::OnOffsetApply(Off offset) { ...@@ -122,12 +122,12 @@ void A64_B_BL::OnOffsetApply(Off offset) {
ENCODE_OFFSET(26, 2); ENCODE_OFFSET(26, 2);
} }
void A64_B_BL::Disassembler() { void A64_B_BL::Disassemble() {
DECODE_OP; DECODE_OP;
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void A64_B_BL::Assembler() { void A64_B_BL::Assemble() {
SET_OPCODE(B_BL); SET_OPCODE(B_BL);
ENCODE_OP; ENCODE_OP;
ENCODE_OFFSET(26, 2); ENCODE_OFFSET(26, 2);
...@@ -153,7 +153,7 @@ Off A64_CBZ_CBNZ::GetImmPCOffset() { ...@@ -153,7 +153,7 @@ Off A64_CBZ_CBNZ::GetImmPCOffset() {
return DECODE_OFFSET(19, 2); return DECODE_OFFSET(19, 2);
} }
void A64_CBZ_CBNZ::Disassembler() { void A64_CBZ_CBNZ::Disassemble() {
DECODE_OP; DECODE_OP;
if (Get()->sf == 1) { if (Get()->sf == 1) {
DECODE_RT(XReg); DECODE_RT(XReg);
...@@ -163,7 +163,7 @@ void A64_CBZ_CBNZ::Disassembler() { ...@@ -163,7 +163,7 @@ void A64_CBZ_CBNZ::Disassembler() {
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void A64_CBZ_CBNZ::Assembler() { void A64_CBZ_CBNZ::Assemble() {
SET_OPCODE(CBZ_CBNZ); SET_OPCODE(CBZ_CBNZ);
ENCODE_OP; ENCODE_OP;
ENCODE_RT; ENCODE_RT;
...@@ -193,12 +193,12 @@ Off A64_B_COND::GetImmPCOffset() { ...@@ -193,12 +193,12 @@ Off A64_B_COND::GetImmPCOffset() {
return DECODE_OFFSET(19, 2); return DECODE_OFFSET(19, 2);
} }
void A64_B_COND::Disassembler() { void A64_B_COND::Disassemble() {
DECODE_COND; DECODE_COND;
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void A64_B_COND::Assembler() { void A64_B_COND::Assemble() {
SET_OPCODE(B_COND); SET_OPCODE(B_COND);
ENCODE_COND; ENCODE_COND;
ENCODE_OFFSET(19, 2); ENCODE_OFFSET(19, 2);
...@@ -230,7 +230,7 @@ Off A64_TBZ_TBNZ::GetImmPCOffset() { ...@@ -230,7 +230,7 @@ Off A64_TBZ_TBNZ::GetImmPCOffset() {
return DECODE_OFFSET(14, 2); return DECODE_OFFSET(14, 2);
} }
void A64_TBZ_TBNZ::Disassembler() { void A64_TBZ_TBNZ::Disassemble() {
bit = COMBINE(Get()->b5, Get()->b40, 5); bit = COMBINE(Get()->b5, Get()->b40, 5);
if (Get()->b5 == 1) { if (Get()->b5 == 1) {
DECODE_RT(XReg); DECODE_RT(XReg);
...@@ -241,7 +241,7 @@ void A64_TBZ_TBNZ::Disassembler() { ...@@ -241,7 +241,7 @@ void A64_TBZ_TBNZ::Disassembler() {
offset = GetImmPCOffset(); offset = GetImmPCOffset();
} }
void A64_TBZ_TBNZ::Assembler() { void A64_TBZ_TBNZ::Assemble() {
SET_OPCODE(TBZ_TBNZ); SET_OPCODE(TBZ_TBNZ);
ENCODE_OP; ENCODE_OP;
Get()->b5 = rt->isX() ? 1 : 0; Get()->b5 = rt->isX() ? 1 : 0;
...@@ -277,7 +277,7 @@ void A64_LDR_LIT::OnOffsetApply(Off offset) { ...@@ -277,7 +277,7 @@ void A64_LDR_LIT::OnOffsetApply(Off offset) {
ENCODE_OFFSET(19, 2); ENCODE_OFFSET(19, 2);
} }
void A64_LDR_LIT::Disassembler() { void A64_LDR_LIT::Disassemble() {
DECODE_OP; DECODE_OP;
offset = GetImmPCOffset(); offset = GetImmPCOffset();
if (op == LDR_W) { if (op == LDR_W) {
...@@ -287,7 +287,7 @@ void A64_LDR_LIT::Disassembler() { ...@@ -287,7 +287,7 @@ void A64_LDR_LIT::Disassembler() {
} }
} }
void A64_LDR_LIT::Assembler() { void A64_LDR_LIT::Assemble() {
SET_OPCODE(LDR_LIT); SET_OPCODE(LDR_LIT);
ENCODE_OP; ENCODE_OP;
ENCODE_RT; ENCODE_RT;
...@@ -301,12 +301,12 @@ A64_BR_BLR_RET::A64_BR_BLR_RET(void *inst) : InstructionA64(inst) {} ...@@ -301,12 +301,12 @@ A64_BR_BLR_RET::A64_BR_BLR_RET(void *inst) : InstructionA64(inst) {}
A64_BR_BLR_RET::A64_BR_BLR_RET(A64_BR_BLR_RET::OP op, XRegister &rn) : op(op), rn(&rn) {} A64_BR_BLR_RET::A64_BR_BLR_RET(A64_BR_BLR_RET::OP op, XRegister &rn) : op(op), rn(&rn) {}
void A64_BR_BLR_RET::Disassembler() { void A64_BR_BLR_RET::Disassemble() {
DECODE_RN(XReg); DECODE_RN(XReg);
DECODE_OP; DECODE_OP;
} }
void A64_BR_BLR_RET::Assembler() { void A64_BR_BLR_RET::Assemble() {
SET_OPCODE_MULTI(BR_BLR_RET, 1); SET_OPCODE_MULTI(BR_BLR_RET, 1);
SET_OPCODE_MULTI(BR_BLR_RET, 2); SET_OPCODE_MULTI(BR_BLR_RET, 2);
SET_OPCODE_MULTI(BR_BLR_RET, 3); SET_OPCODE_MULTI(BR_BLR_RET, 3);
...@@ -322,7 +322,7 @@ A64_STR_IMM::A64_STR_IMM(void *inst) : A64LoadAndStoreImm(inst) {} ...@@ -322,7 +322,7 @@ A64_STR_IMM::A64_STR_IMM(void *inst) : A64LoadAndStoreImm(inst) {}
A64_STR_IMM::A64_STR_IMM(RegisterA64 &rt, const MemOperand &operand) : A64LoadAndStoreImm(&rt, operand) { A64_STR_IMM::A64_STR_IMM(RegisterA64 &rt, const MemOperand &operand) : A64LoadAndStoreImm(&rt, operand) {
} }
void A64_STR_IMM::Disassembler() { void A64_STR_IMM::Disassemble() {
regSize = RegSize(Get()->size); regSize = RegSize(Get()->size);
switch (regSize) { switch (regSize) {
case Size64: case Size64:
...@@ -358,7 +358,7 @@ void A64_STR_IMM::Disassembler() { ...@@ -358,7 +358,7 @@ void A64_STR_IMM::Disassembler() {
operand.offset_ = offset; operand.offset_ = offset;
} }
void A64_STR_IMM::Assembler() { void A64_STR_IMM::Assemble() {
SET_OPCODE(STR_IMM); SET_OPCODE(STR_IMM);
Get()->rt = rt->Code(); Get()->rt = rt->Code();
Get()->rn = operand.base_->Code(); Get()->rn = operand.base_->Code();
...@@ -395,7 +395,7 @@ A64_STR_UIMM::A64_STR_UIMM(void *inst) : A64LoadAndStoreImm(inst) {} ...@@ -395,7 +395,7 @@ A64_STR_UIMM::A64_STR_UIMM(void *inst) : A64LoadAndStoreImm(inst) {}
A64_STR_UIMM::A64_STR_UIMM(RegisterA64 &rt, const MemOperand &operand) : A64LoadAndStoreImm(&rt, operand) { A64_STR_UIMM::A64_STR_UIMM(RegisterA64 &rt, const MemOperand &operand) : A64LoadAndStoreImm(&rt, operand) {
} }
void A64_STR_UIMM::Disassembler() { void A64_STR_UIMM::Disassemble() {
regSize = RegSize(Get()->size); regSize = RegSize(Get()->size);
switch (regSize) { switch (regSize) {
case Size64: case Size64:
...@@ -416,7 +416,7 @@ void A64_STR_UIMM::Disassembler() { ...@@ -416,7 +416,7 @@ void A64_STR_UIMM::Disassembler() {
operand.offset_ = offset; operand.offset_ = offset;
} }
void A64_STR_UIMM::Assembler() { void A64_STR_UIMM::Assemble() {
SET_OPCODE(STR_UIMM); SET_OPCODE(STR_UIMM);
ENCODE_RT; ENCODE_RT;
Get()->rn = operand.base_->Code(); Get()->rn = operand.base_->Code();
...@@ -438,7 +438,7 @@ A64_MOV_REG::A64_MOV_REG(void *inst) : InstructionA64(inst) { ...@@ -438,7 +438,7 @@ A64_MOV_REG::A64_MOV_REG(void *inst) : InstructionA64(inst) {
A64_MOV_REG::A64_MOV_REG(RegisterA64 &rd, RegisterA64 &rm) : rd(&rd), rm(&rm) { A64_MOV_REG::A64_MOV_REG(RegisterA64 &rd, RegisterA64 &rm) : rd(&rd), rm(&rm) {
} }
void A64_MOV_REG::Disassembler() { void A64_MOV_REG::Disassemble() {
if (Get()->sf == 1) { if (Get()->sf == 1) {
DECODE_RD(XReg); DECODE_RD(XReg);
DECODE_RM(XReg); DECODE_RM(XReg);
...@@ -448,7 +448,7 @@ void A64_MOV_REG::Disassembler() { ...@@ -448,7 +448,7 @@ void A64_MOV_REG::Disassembler() {
} }
} }
void A64_MOV_REG::Assembler() { void A64_MOV_REG::Assemble() {
SET_OPCODE_MULTI(MOV_REG, 1); SET_OPCODE_MULTI(MOV_REG, 1);
SET_OPCODE_MULTI(MOV_REG, 2); SET_OPCODE_MULTI(MOV_REG, 2);
Get()->sf = rd->isX() ? 1 : 0; Get()->sf = rd->isX() ? 1 : 0;
...@@ -462,7 +462,7 @@ A64_SUB_EXT_REG::A64_SUB_EXT_REG(RegisterA64 &rd, RegisterA64 &rn, const Operand ...@@ -462,7 +462,7 @@ A64_SUB_EXT_REG::A64_SUB_EXT_REG(RegisterA64 &rd, RegisterA64 &rn, const Operand
FlagsUpdate flagsUpdate) : rd(&rd), rn(&rn), operand(operand), FlagsUpdate flagsUpdate) : rd(&rd), rn(&rn), operand(operand),
flagsUpdate(flagsUpdate) {} flagsUpdate(flagsUpdate) {}
void A64_SUB_EXT_REG::Disassembler() { void A64_SUB_EXT_REG::Disassemble() {
flagsUpdate = FlagsUpdate(Get()->S); flagsUpdate = FlagsUpdate(Get()->S);
if (Get()->sf == 1) { if (Get()->sf == 1) {
DECODE_RD(XReg); DECODE_RD(XReg);
...@@ -478,7 +478,7 @@ void A64_SUB_EXT_REG::Disassembler() { ...@@ -478,7 +478,7 @@ void A64_SUB_EXT_REG::Disassembler() {
operand.shift_ = Shift(Get()->imm3); operand.shift_ = Shift(Get()->imm3);
} }
void A64_SUB_EXT_REG::Assembler() { void A64_SUB_EXT_REG::Assemble() {
SET_OPCODE_MULTI(SUB_EXT_REG, 1); SET_OPCODE_MULTI(SUB_EXT_REG, 1);
SET_OPCODE_MULTI(SUB_EXT_REG, 2); SET_OPCODE_MULTI(SUB_EXT_REG, 2);
Get()->S = flagsUpdate; Get()->S = flagsUpdate;
...@@ -498,13 +498,13 @@ A64_EXCEPTION_GEN::A64_EXCEPTION_GEN(void* inst) : InstructionA64(inst) { ...@@ -498,13 +498,13 @@ A64_EXCEPTION_GEN::A64_EXCEPTION_GEN(void* inst) : InstructionA64(inst) {
A64_EXCEPTION_GEN::A64_EXCEPTION_GEN(A64_EXCEPTION_GEN::OP op, ExceptionLevel el, U16 imme) : op( A64_EXCEPTION_GEN::A64_EXCEPTION_GEN(A64_EXCEPTION_GEN::OP op, ExceptionLevel el, U16 imme) : op(
op), el(el), imme(imme) {} op), el(el), imme(imme) {}
void A64_EXCEPTION_GEN::Disassembler() { void A64_EXCEPTION_GEN::Disassemble() {
DECODE_OP; DECODE_OP;
el = ExceptionLevel(Get()->ll); el = ExceptionLevel(Get()->ll);
imme = static_cast<U16>(Get()->imm16); imme = static_cast<U16>(Get()->imm16);
} }
void A64_EXCEPTION_GEN::Assembler() { void A64_EXCEPTION_GEN::Assemble() {
SET_OPCODE_MULTI(EXCEPTION_GEN, 1); SET_OPCODE_MULTI(EXCEPTION_GEN, 1);
SET_OPCODE_MULTI(EXCEPTION_GEN, 2); SET_OPCODE_MULTI(EXCEPTION_GEN, 2);
ENCODE_OP; ENCODE_OP;
...@@ -525,7 +525,7 @@ A64_LDR_IMM::A64_LDR_IMM(void *inst) : A64LoadAndStoreImm(inst) { ...@@ -525,7 +525,7 @@ A64_LDR_IMM::A64_LDR_IMM(void *inst) : A64LoadAndStoreImm(inst) {
A64_LDR_IMM::A64_LDR_IMM(RegisterA64 &rt, const MemOperand &operand) : A64LoadAndStoreImm(&rt, A64_LDR_IMM::A64_LDR_IMM(RegisterA64 &rt, const MemOperand &operand) : A64LoadAndStoreImm(&rt,
operand) {} operand) {}
void A64_LDR_IMM::Disassembler() { void A64_LDR_IMM::Disassemble() {
regSize = RegSize(Get()->size); regSize = RegSize(Get()->size);
switch (regSize) { switch (regSize) {
case Size64: case Size64:
...@@ -561,7 +561,7 @@ void A64_LDR_IMM::Disassembler() { ...@@ -561,7 +561,7 @@ void A64_LDR_IMM::Disassembler() {
operand.offset_ = offset; operand.offset_ = offset;
} }
void A64_LDR_IMM::Assembler() { void A64_LDR_IMM::Assemble() {
SET_OPCODE(LDR_IMM); SET_OPCODE(LDR_IMM);
Get()->rt = rt->Code(); Get()->rt = rt->Code();
Get()->rn = operand.base_->Code(); Get()->rn = operand.base_->Code();
...@@ -600,7 +600,7 @@ A64_LDR_UIMM::A64_LDR_UIMM(void *inst) : A64LoadAndStoreImm(&inst) { ...@@ -600,7 +600,7 @@ A64_LDR_UIMM::A64_LDR_UIMM(void *inst) : A64LoadAndStoreImm(&inst) {
A64_LDR_UIMM::A64_LDR_UIMM(RegisterA64 &rt, const MemOperand &operand) : A64LoadAndStoreImm(&rt, A64_LDR_UIMM::A64_LDR_UIMM(RegisterA64 &rt, const MemOperand &operand) : A64LoadAndStoreImm(&rt,
operand) {} operand) {}
void A64_LDR_UIMM::Disassembler() { void A64_LDR_UIMM::Disassemble() {
regSize = RegSize(Get()->size); regSize = RegSize(Get()->size);
switch (regSize) { switch (regSize) {
case Size64: case Size64:
...@@ -621,7 +621,7 @@ void A64_LDR_UIMM::Disassembler() { ...@@ -621,7 +621,7 @@ void A64_LDR_UIMM::Disassembler() {
operand.offset_ = offset; operand.offset_ = offset;
} }
void A64_LDR_UIMM::Assembler() { void A64_LDR_UIMM::Assemble() {
SET_OPCODE(LDR_UIMM); SET_OPCODE(LDR_UIMM);
Get()->rt = rt->Code(); Get()->rt = rt->Code();
Get()->rn = operand.base_->Code(); Get()->rn = operand.base_->Code();
...@@ -643,7 +643,7 @@ A64_LDRSW_IMM::A64_LDRSW_IMM(void *inst) : A64_LDR_IMM(inst) {} ...@@ -643,7 +643,7 @@ A64_LDRSW_IMM::A64_LDRSW_IMM(void *inst) : A64_LDR_IMM(inst) {}
A64_LDRSW_IMM::A64_LDRSW_IMM(RegisterA64 &rt, const MemOperand &operand) : A64_LDR_IMM(rt, A64_LDRSW_IMM::A64_LDRSW_IMM(RegisterA64 &rt, const MemOperand &operand) : A64_LDR_IMM(rt,
operand) {} operand) {}
void A64_LDRSW_IMM::Disassembler() { void A64_LDRSW_IMM::Disassemble() {
rt = XReg(static_cast<U8>(Get()->rt)); rt = XReg(static_cast<U8>(Get()->rt));
addrMode = AdMod(Get()->addrmode); addrMode = AdMod(Get()->addrmode);
switch (addrMode) { switch (addrMode) {
...@@ -668,7 +668,7 @@ void A64_LDRSW_IMM::Disassembler() { ...@@ -668,7 +668,7 @@ void A64_LDRSW_IMM::Disassembler() {
operand.base_ = XReg(static_cast<U8>(Get()->rn)); operand.base_ = XReg(static_cast<U8>(Get()->rn));
} }
void A64_LDRSW_IMM::Assembler() { void A64_LDRSW_IMM::Assemble() {
SET_OPCODE(LDRSW_IMM); SET_OPCODE(LDRSW_IMM);
Get()->size = Size32; Get()->size = Size32;
Get()->rt = rt->Code(); Get()->rt = rt->Code();
...@@ -698,7 +698,7 @@ A64_LDRSW_UIMM::A64_LDRSW_UIMM(void *inst) : A64_LDR_UIMM(inst) {} ...@@ -698,7 +698,7 @@ A64_LDRSW_UIMM::A64_LDRSW_UIMM(void *inst) : A64_LDR_UIMM(inst) {}
A64_LDRSW_UIMM::A64_LDRSW_UIMM(XRegister &rt, const MemOperand &operand) : A64_LDR_UIMM(rt, A64_LDRSW_UIMM::A64_LDRSW_UIMM(XRegister &rt, const MemOperand &operand) : A64_LDR_UIMM(rt,
operand) {} operand) {}
void A64_LDRSW_UIMM::Disassembler() { void A64_LDRSW_UIMM::Disassemble() {
DECODE_RT(XReg); DECODE_RT(XReg);
operand.base_ = XReg(static_cast<U8>(Get()->rn)); operand.base_ = XReg(static_cast<U8>(Get()->rn));
operand.addr_mode_ = AddrMode::Offset; operand.addr_mode_ = AddrMode::Offset;
...@@ -707,7 +707,7 @@ void A64_LDRSW_UIMM::Disassembler() { ...@@ -707,7 +707,7 @@ void A64_LDRSW_UIMM::Disassembler() {
operand.offset_ = offset; operand.offset_ = offset;
} }
void A64_LDRSW_UIMM::Assembler() { void A64_LDRSW_UIMM::Assemble() {
SET_OPCODE(LDRSW_UIMM); SET_OPCODE(LDRSW_UIMM);
Get()->size = Size32; Get()->size = Size32;
ENCODE_RT; ENCODE_RT;
...@@ -724,7 +724,7 @@ A64_STP_LDP::A64_STP_LDP(OP op, RegisterA64 &rt1, RegisterA64 &rt2, const MemOpe ...@@ -724,7 +724,7 @@ A64_STP_LDP::A64_STP_LDP(OP op, RegisterA64 &rt1, RegisterA64 &rt2, const MemOpe
rt2(&rt2), rt2(&rt2),
operand(operand) {} operand(operand) {}
void A64_STP_LDP::Disassembler() { void A64_STP_LDP::Disassemble() {
DECODE_OP; DECODE_OP;
RegSize s = RegSize(Get()->size); RegSize s = RegSize(Get()->size);
if (s == Size64) { if (s == Size64) {
...@@ -751,7 +751,7 @@ void A64_STP_LDP::Disassembler() { ...@@ -751,7 +751,7 @@ void A64_STP_LDP::Disassembler() {
} }
} }
void A64_STP_LDP::Assembler() { void A64_STP_LDP::Assemble() {
SET_OPCODE(STP_LDP); SET_OPCODE(STP_LDP);
ENCODE_OP; ENCODE_OP;
Get()->size = rt1->isX() ? Size64 : Size32; Get()->size = rt1->isX() ? Size64 : Size32;
...@@ -781,7 +781,7 @@ A64_ADD_SUB_IMM::A64_ADD_SUB_IMM(void *inst) : InstructionA64(&inst) { ...@@ -781,7 +781,7 @@ A64_ADD_SUB_IMM::A64_ADD_SUB_IMM(void *inst) : InstructionA64(&inst) {
A64_ADD_SUB_IMM::A64_ADD_SUB_IMM(A64_ADD_SUB_IMM::OP op, A64_ADD_SUB_IMM::S sign, RegisterA64 &rd, A64_ADD_SUB_IMM::A64_ADD_SUB_IMM(A64_ADD_SUB_IMM::OP op, A64_ADD_SUB_IMM::S sign, RegisterA64 &rd,
const Operand &operand) : op(op), sign(sign), rd(&rd), operand(operand) {} const Operand &operand) : op(op), sign(sign), rd(&rd), operand(operand) {}
void A64_ADD_SUB_IMM::Disassembler() { void A64_ADD_SUB_IMM::Disassemble() {
DECODE_OP; DECODE_OP;
if (Get()->sf == Size64) { if (Get()->sf == Size64) {
DECODE_RD(XReg); DECODE_RD(XReg);
...@@ -801,7 +801,7 @@ void A64_ADD_SUB_IMM::Disassembler() { ...@@ -801,7 +801,7 @@ void A64_ADD_SUB_IMM::Disassembler() {
} }
} }
void A64_ADD_SUB_IMM::Assembler() { void A64_ADD_SUB_IMM::Assemble() {
SET_OPCODE(ADD_SUB_IMM); SET_OPCODE(ADD_SUB_IMM);
ENCODE_OP; ENCODE_OP;
ENCODE_RD; ENCODE_RD;
...@@ -824,13 +824,13 @@ A64_MSR_MRS::A64_MSR_MRS(void *inst) : InstructionA64(&inst) { ...@@ -824,13 +824,13 @@ A64_MSR_MRS::A64_MSR_MRS(void *inst) : InstructionA64(&inst) {
A64_MSR_MRS::A64_MSR_MRS(OP op, SystemRegister &systemRegister, RegisterA64 &rt) : op(op), system_reg( A64_MSR_MRS::A64_MSR_MRS(OP op, SystemRegister &systemRegister, RegisterA64 &rt) : op(op), system_reg(
&systemRegister), rt(&rt) {} &systemRegister), rt(&rt) {}
void A64_MSR_MRS::Disassembler() { void A64_MSR_MRS::Disassemble() {
DECODE_OP; DECODE_OP;
DECODE_RT(XReg); DECODE_RT(XReg);
system_reg->value = static_cast<U16>(Get()->sysreg); system_reg->value = static_cast<U16>(Get()->sysreg);
} }
void A64_MSR_MRS::Assembler() { void A64_MSR_MRS::Assemble() {
SET_OPCODE(MSR_MRS); SET_OPCODE(MSR_MRS);
ENCODE_OP; ENCODE_OP;
ENCODE_RT; ENCODE_RT;
......
...@@ -217,9 +217,9 @@ namespace SandHook { ...@@ -217,9 +217,9 @@ namespace SandHook {
Addr GetImmPCOffsetTarget() override; Addr GetImmPCOffsetTarget() override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -254,9 +254,9 @@ namespace SandHook { ...@@ -254,9 +254,9 @@ namespace SandHook {
DEFINE_IS(MOV_WIDE) DEFINE_IS(MOV_WIDE)
void Assembler() override; void Assemble() override;
void Disassembler() override; void Disassemble() override;
public: public:
//can be 16/32/64/128 //can be 16/32/64/128
...@@ -297,9 +297,9 @@ namespace SandHook { ...@@ -297,9 +297,9 @@ namespace SandHook {
void OnOffsetApply(Off offset) override; void OnOffsetApply(Off offset) override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
...@@ -328,9 +328,9 @@ namespace SandHook { ...@@ -328,9 +328,9 @@ namespace SandHook {
Off GetImmPCOffset() override; Off GetImmPCOffset() override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -354,9 +354,9 @@ namespace SandHook { ...@@ -354,9 +354,9 @@ namespace SandHook {
void OnOffsetApply(Off offset) override; void OnOffsetApply(Off offset) override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
Condition condition; Condition condition;
...@@ -385,9 +385,9 @@ namespace SandHook { ...@@ -385,9 +385,9 @@ namespace SandHook {
Off GetImmPCOffset() override; Off GetImmPCOffset() override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -419,9 +419,9 @@ namespace SandHook { ...@@ -419,9 +419,9 @@ namespace SandHook {
void OnOffsetApply(Off offset) override; void OnOffsetApply(Off offset) override;
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -445,9 +445,9 @@ namespace SandHook { ...@@ -445,9 +445,9 @@ namespace SandHook {
DEFINE_IS_EXT(BR_BLR_RET, TEST_INST_OPCODE(BR_BLR_RET, 1) && TEST_INST_OPCODE(BR_BLR_RET, 2) && TEST_INST_OPCODE(BR_BLR_RET,3)) DEFINE_IS_EXT(BR_BLR_RET, TEST_INST_OPCODE(BR_BLR_RET, 1) && TEST_INST_OPCODE(BR_BLR_RET, 2) && TEST_INST_OPCODE(BR_BLR_RET,3))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -496,9 +496,9 @@ namespace SandHook { ...@@ -496,9 +496,9 @@ namespace SandHook {
DEFINE_IS(STR_IMM) DEFINE_IS(STR_IMM)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
}; };
...@@ -512,9 +512,9 @@ namespace SandHook { ...@@ -512,9 +512,9 @@ namespace SandHook {
DEFINE_IS(STR_UIMM) DEFINE_IS(STR_UIMM)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
}; };
...@@ -527,9 +527,9 @@ namespace SandHook { ...@@ -527,9 +527,9 @@ namespace SandHook {
DEFINE_IS_EXT(MOV_REG, TEST_INST_OPCODE(MOV_REG, 1) && TEST_INST_OPCODE(MOV_REG, 2)) DEFINE_IS_EXT(MOV_REG, TEST_INST_OPCODE(MOV_REG, 1) && TEST_INST_OPCODE(MOV_REG, 2))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
RegisterA64* rd; RegisterA64* rd;
...@@ -547,9 +547,9 @@ namespace SandHook { ...@@ -547,9 +547,9 @@ namespace SandHook {
DEFINE_IS_EXT(SUB_EXT_REG, TEST_INST_OPCODE(SUB_EXT_REG, 1) && TEST_INST_OPCODE(SUB_EXT_REG, 2)) DEFINE_IS_EXT(SUB_EXT_REG, TEST_INST_OPCODE(SUB_EXT_REG, 1) && TEST_INST_OPCODE(SUB_EXT_REG, 2))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
...@@ -576,9 +576,9 @@ namespace SandHook { ...@@ -576,9 +576,9 @@ namespace SandHook {
DEFINE_IS_EXT(EXCEPTION_GEN, TEST_INST_OPCODE(EXCEPTION_GEN, 1) && TEST_INST_OPCODE(EXCEPTION_GEN, 2)) DEFINE_IS_EXT(EXCEPTION_GEN, TEST_INST_OPCODE(EXCEPTION_GEN, 1) && TEST_INST_OPCODE(EXCEPTION_GEN, 2))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -608,9 +608,9 @@ namespace SandHook { ...@@ -608,9 +608,9 @@ namespace SandHook {
DEFINE_IS(LDR_IMM) DEFINE_IS(LDR_IMM)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
}; };
...@@ -623,9 +623,9 @@ namespace SandHook { ...@@ -623,9 +623,9 @@ namespace SandHook {
DEFINE_IS(LDR_UIMM) DEFINE_IS(LDR_UIMM)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
}; };
DEFINE_INST_EXT(LDRSW_IMM, LDR_IMM) { DEFINE_INST_EXT(LDRSW_IMM, LDR_IMM) {
...@@ -638,9 +638,9 @@ namespace SandHook { ...@@ -638,9 +638,9 @@ namespace SandHook {
DEFINE_IS_EXT(LDRSW_IMM, TEST_INST_FIELD(opcode, OPCODE_A64(LDRSW_IMM)) && DEFINE_IS_EXT(LDRSW_IMM, TEST_INST_FIELD(opcode, OPCODE_A64(LDRSW_IMM)) &&
TEST_INST_FIELD(size , Size32)) TEST_INST_FIELD(size , Size32))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
}; };
...@@ -655,9 +655,9 @@ namespace SandHook { ...@@ -655,9 +655,9 @@ namespace SandHook {
DEFINE_IS_EXT(LDRSW_UIMM, TEST_INST_FIELD(opcode, OPCODE_A64(LDRSW_UIMM)) && DEFINE_IS_EXT(LDRSW_UIMM, TEST_INST_FIELD(opcode, OPCODE_A64(LDRSW_UIMM)) &&
TEST_INST_FIELD(size, Size32)) TEST_INST_FIELD(size, Size32))
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
}; };
...@@ -685,9 +685,9 @@ namespace SandHook { ...@@ -685,9 +685,9 @@ namespace SandHook {
DEFINE_IS(STP_LDP) DEFINE_IS(STP_LDP)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -721,9 +721,9 @@ namespace SandHook { ...@@ -721,9 +721,9 @@ namespace SandHook {
DEFINE_IS(ADD_SUB_IMM) DEFINE_IS(ADD_SUB_IMM)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
...@@ -747,9 +747,9 @@ namespace SandHook { ...@@ -747,9 +747,9 @@ namespace SandHook {
DEFINE_IS(MSR_MRS) DEFINE_IS(MSR_MRS)
void Disassembler() override; void Disassemble() override;
void Assembler() override; void Assemble() override;
public: public:
OP op; OP op;
......
...@@ -85,11 +85,11 @@ namespace SandHook { ...@@ -85,11 +85,11 @@ namespace SandHook {
label->AddBind(this); label->AddBind(this);
} }
virtual void Disassembler() { virtual void Disassemble() {
backup_ = *this->pc_; backup_ = *this->pc_;
} }
virtual void Assembler() { virtual void Assemble() {
*this->pc_ = backup_; *this->pc_ = backup_;
} }
......
...@@ -46,7 +46,7 @@ void CodeContainer::commit() { ...@@ -46,7 +46,7 @@ void CodeContainer::commit() {
(*unit)->Set(reinterpret_cast<Base*>(pcNow)); (*unit)->Set(reinterpret_cast<Base*>(pcNow));
} }
if ((*unit)->UnitType() == UnitInst) { if ((*unit)->UnitType() == UnitInst) {
reinterpret_cast<BaseInst*>(*unit)->Assembler(); reinterpret_cast<BaseInst*>(*unit)->Assemble();
} }
pcNow += (*unit)->Size(); pcNow += (*unit)->Size();
} }
......
...@@ -100,7 +100,7 @@ void breakCallback(REG regs[]) { ...@@ -100,7 +100,7 @@ void breakCallback(REG regs[]) {
class Visitor : public InstVisitor { class Visitor : public InstVisitor {
bool Visit(Unit<Base> *unit, void *pc) override { bool Visit(Unit<Base> *unit, void *pc) override {
BaseInst* instruction = reinterpret_cast<BaseInst *>(unit); BaseInst* instruction = reinterpret_cast<BaseInst *>(unit);
instruction->Assembler(); instruction->Assemble();
return true; return true;
} }
}; };
......
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