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SandHook
Commits
612980be
Commit
612980be
authored
Jul 01, 2019
by
swift_gan
Committed by
swift_gan
Jul 01, 2019
Browse files
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Plain Diff
[Reconstitution]tweak typo
parent
c2a9a03f
Expand all
Hide whitespace changes
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Side-by-side
Showing
12 changed files
with
163 additions
and
163 deletions
+163
-163
inst_arm32.cpp
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_arm32.cpp
+1
-1
inst_arm32.h
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_arm32.h
+1
-1
inst_t16.cpp
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.cpp
+28
-28
inst_t16.h
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.h
+28
-28
inst_t32.cpp
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.cpp
+10
-10
inst_t32.h
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.h
+10
-10
decoder_arm64.cpp
...ok/src/main/cpp/archs/arm/arm64/decoder/decoder_arm64.cpp
+1
-1
inst_arm64.cpp
nativehook/src/main/cpp/archs/arm/arm64/inst/inst_arm64.cpp
+40
-40
inst_arm64.h
nativehook/src/main/cpp/archs/arm/arm64/inst/inst_arm64.h
+40
-40
instruction.h
nativehook/src/main/cpp/asm/instruction.h
+2
-2
assembler.cpp
nativehook/src/main/cpp/assembler/assembler.cpp
+1
-1
sandhook_native.cpp
nativehook/src/main/cpp/sandhook_native.cpp
+1
-1
No files found.
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_arm32.cpp
View file @
612980be
...
...
@@ -42,7 +42,7 @@
//}
//
//
//void A64_STR_IMM::Assemble
r
() {
//void A64_STR_IMM::Assemble() {
// INST_DCHECK(condition, Condition::nv)
//
//}
\ No newline at end of file
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_arm32.h
View file @
612980be
...
...
@@ -25,7 +25,7 @@ namespace SandHook {
//
// void DisAssembler(STRUCT_A64(STR_IMM) *inst) override;
//
// void Assemble
r
() override;
// void Assemble() override;
//
// AddrMode getAddrMode() {
// return operand.addr_mode_;
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.cpp
View file @
612980be
...
...
@@ -35,11 +35,11 @@ Off T16_B::GetImmPCOffset() {
return
DECODE_OFFSET
(
11
,
1
);
}
void
T16_B
::
Disassemble
r
()
{
void
T16_B
::
Disassemble
()
{
offset
=
GetImmPCOffset
();
}
void
T16_B
::
Assemble
r
()
{
void
T16_B
::
Assemble
()
{
SET_OPCODE
(
B
);
DECODE_OFFSET
(
11
,
1
);
}
...
...
@@ -62,12 +62,12 @@ T16_B_COND::T16_B_COND(Condition condition, Label *label) {
BindLabel
(
label
);
}
void
T16_B_COND
::
Disassemble
r
()
{
void
T16_B_COND
::
Disassemble
()
{
DECODE_COND
;
offset
=
GetImmPCOffset
();
}
void
T16_B_COND
::
Assemble
r
()
{
void
T16_B_COND
::
Assemble
()
{
SET_OPCODE
(
B_COND
);
ENCODE_COND
;
ENCODE_OFFSET
(
8
,
1
);
...
...
@@ -89,12 +89,12 @@ T16_BX_BLX::T16_BX_BLX(void *inst) : T16_INST_PC_REL(inst) {}
T16_BX_BLX
::
T16_BX_BLX
(
T16_BX_BLX
::
OP
op
,
RegisterA32
&
rm
)
:
op
(
op
),
rm
(
&
rm
)
{}
void
T16_BX_BLX
::
Disassemble
r
()
{
void
T16_BX_BLX
::
Disassemble
()
{
DECODE_OP
;
DECODE_RM
(
Reg
);
}
void
T16_BX_BLX
::
Assemble
r
()
{
void
T16_BX_BLX
::
Assemble
()
{
SET_OPCODE_MULTI
(
BX_BLX
,
1
);
SET_OPCODE_MULTI
(
BX_BLX
,
2
);
ENCODE_OP
;
...
...
@@ -116,13 +116,13 @@ Off T16_CBZ_CBNZ::GetImmPCOffset() {
return
COMBINE
(
Get
()
->
i
,
Get
()
->
imm5
,
5
)
<<
2
;
}
void
T16_CBZ_CBNZ
::
Disassemble
r
()
{
void
T16_CBZ_CBNZ
::
Disassemble
()
{
offset
=
GetImmPCOffset
();
DECODE_RN
(
Reg
);
DECODE_OP
;
}
void
T16_CBZ_CBNZ
::
Assemble
r
()
{
void
T16_CBZ_CBNZ
::
Assemble
()
{
SET_OPCODE_MULTI
(
CBZ_CBNZ
,
1
);
SET_OPCODE_MULTI
(
CBZ_CBNZ
,
2
);
SET_OPCODE_MULTI
(
CBZ_CBNZ
,
3
);
...
...
@@ -155,12 +155,12 @@ void T16_LDR_LIT::OnOffsetApply(Off offset) {
ENCODE_OFFSET
(
8
,
2
);
}
void
T16_LDR_LIT
::
Disassemble
r
()
{
void
T16_LDR_LIT
::
Disassemble
()
{
DECODE_RT
(
Reg
);
offset
=
GetImmPCOffset
();
}
void
T16_LDR_LIT
::
Assemble
r
()
{
void
T16_LDR_LIT
::
Assemble
()
{
SET_OPCODE
(
LDR_LIT
);
ENCODE_RT
;
ENCODE_OFFSET
(
8
,
2
);
...
...
@@ -174,12 +174,12 @@ T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(void *inst) : InstructionT16(inst) {}
T16_ADD_IMM_RDN
::
T16_ADD_IMM_RDN
(
RegisterA32
*
rdn
,
U8
imm8
)
:
rdn
(
rdn
),
imm8
(
imm8
)
{}
void
T16_ADD_IMM_RDN
::
Disassemble
r
()
{
void
T16_ADD_IMM_RDN
::
Disassemble
()
{
rdn
=
Reg
(
Get
()
->
rdn
);
imm8
=
Get
()
->
imm8
;
}
void
T16_ADD_IMM_RDN
::
Assemble
r
()
{
void
T16_ADD_IMM_RDN
::
Assemble
()
{
SET_OPCODE
(
ADD_IMM_RDN
);
Get
()
->
imm8
=
imm8
;
Get
()
->
rdn
=
rdn
->
Code
();
...
...
@@ -211,13 +211,13 @@ void T16_ADR::OnOffsetApply(Off offset) {
Get
()
->
imm8
=
(
U32
)
offset
>>
2
;
}
void
T16_ADR
::
Disassemble
r
()
{
void
T16_ADR
::
Disassemble
()
{
offset
=
GetImmPCOffset
();
DECODE_RD
(
Reg
);
}
void
T16_ADR
::
Assemble
r
()
{
void
T16_ADR
::
Assemble
()
{
SET_OPCODE
(
ADR
);
ENCODE_RD
;
Get
()
->
imm8
=
(
U32
)
offset
>>
2
;
...
...
@@ -228,12 +228,12 @@ T16_CMP_REG::T16_CMP_REG(void *inst) : InstructionT16(inst) {}
T16_CMP_REG
::
T16_CMP_REG
(
RegisterA32
&
rm
,
RegisterA32
&
rn
)
:
rm
(
&
rm
),
rn
(
&
rn
)
{}
void
T16_CMP_REG
::
Disassemble
r
()
{
void
T16_CMP_REG
::
Disassemble
()
{
DECODE_RM
(
Reg
);
DECODE_RN
(
Reg
);
}
void
T16_CMP_REG
::
Assemble
r
()
{
void
T16_CMP_REG
::
Assemble
()
{
SET_BASE_OPCODE
(
DATA_PROC
);
SET_OPCODE
(
CMP_REG
);
ENCODE_RM
;
...
...
@@ -246,12 +246,12 @@ T16_MOV_REG::T16_MOV_REG(void *inst) : InstructionT16(inst) {}
T16_MOV_REG
::
T16_MOV_REG
(
RegisterA32
&
rd
,
RegisterA32
&
rm
)
:
rm
(
&
rm
),
rd
(
&
rd
)
{}
void
T16_MOV_REG
::
Disassemble
r
()
{
void
T16_MOV_REG
::
Disassemble
()
{
DECODE_RM
(
Reg
);
rd
=
Reg
(
static_cast
<
U8
>
(
COMBINE
(
Get
()
->
D
,
Get
()
->
rd
,
3
)));
}
void
T16_MOV_REG
::
Assemble
r
()
{
void
T16_MOV_REG
::
Assemble
()
{
SET_BASE_OPCODE
(
DATA_PROC
);
SET_OPCODE
(
MOV_REG
);
ENCODE_RM
;
...
...
@@ -271,13 +271,13 @@ T16_ADD_REG::T16_ADD_REG(void *inst) : InstructionT16(inst) {}
T16_ADD_REG
::
T16_ADD_REG
(
RegisterA32
*
rd
,
RegisterA32
*
rn
,
RegisterA32
*
rm
)
:
rd
(
rd
),
rn
(
rn
),
rm
(
rm
)
{}
void
T16_ADD_REG
::
Disassemble
r
()
{
void
T16_ADD_REG
::
Disassemble
()
{
DECODE_RD
(
Reg
);
DECODE_RN
(
Reg
);
DECODE_RM
(
Reg
);
}
void
T16_ADD_REG
::
Assemble
r
()
{
void
T16_ADD_REG
::
Assemble
()
{
SET_OPCODE
(
ADD_REG
);
INST_ASSERT
(
rd
->
Code
()
>
7
);
INST_ASSERT
(
rn
->
Code
()
>
7
);
...
...
@@ -293,12 +293,12 @@ T16_CMP_REG_EXT::T16_CMP_REG_EXT(void *inst) : InstructionT16(inst) {}
T16_CMP_REG_EXT
::
T16_CMP_REG_EXT
(
RegisterA32
&
rn
,
RegisterA32
&
rm
)
:
rn
(
&
rn
),
rm
(
&
rm
)
{}
void
T16_CMP_REG_EXT
::
Disassemble
r
()
{
void
T16_CMP_REG_EXT
::
Disassemble
()
{
rn
=
Reg
(
COMBINE
(
Get
()
->
N
,
Get
()
->
rn
,
3
));
DECODE_RM
(
Reg
);
}
void
T16_CMP_REG_EXT
::
Assemble
r
()
{
void
T16_CMP_REG_EXT
::
Assemble
()
{
SET_OPCODE
(
CMP_REG_EXT
);
ENCODE_RM
;
Get
()
->
rn
=
BITS
(
rn
->
Code
(),
0
,
2
);
...
...
@@ -311,11 +311,11 @@ T16_POP::T16_POP(void *inst) : InstructionT16(inst) {}
T16_POP
::
T16_POP
(
const
RegisterList
&
registerList
)
:
registerList
(
registerList
)
{}
void
T16_POP
::
Disassemble
r
()
{
void
T16_POP
::
Disassemble
()
{
registerList
.
SetList
(
COMBINE
(
Get
()
->
P
<<
7
,
Get
()
->
regs
,
8
));
}
void
T16_POP
::
Assemble
r
()
{
void
T16_POP
::
Assemble
()
{
SET_OPCODE
(
POP
);
U16
regs
=
registerList
.
GetList
();
Get
()
->
regs
=
BITS
(
regs
,
0
,
7
);
...
...
@@ -328,11 +328,11 @@ T16_PUSH::T16_PUSH(void *inst) : InstructionT16(inst) {}
T16_PUSH
::
T16_PUSH
(
const
RegisterList
&
registerList
)
:
registerList
(
registerList
)
{}
void
T16_PUSH
::
Disassemble
r
()
{
void
T16_PUSH
::
Disassemble
()
{
registerList
.
SetList
(
COMBINE
(
Get
()
->
M
<<
6
,
Get
()
->
regs
,
8
));
}
void
T16_PUSH
::
Assemble
r
()
{
void
T16_PUSH
::
Assemble
()
{
SET_OPCODE
(
PUSH
);
U16
regs
=
registerList
.
GetList
();
Get
()
->
regs
=
BITS
(
regs
,
0
,
7
);
...
...
@@ -349,12 +349,12 @@ bool T16_ADD_REG_RDN::PcRelate() {
return
*
rm
==
PC
;
}
void
T16_ADD_REG_RDN
::
Disassemble
r
()
{
void
T16_ADD_REG_RDN
::
Disassemble
()
{
DECODE_RM
(
Reg
);
rdn
=
Reg
(
Get
()
->
rdn
);
}
void
T16_ADD_REG_RDN
::
Assemble
r
()
{
void
T16_ADD_REG_RDN
::
Assemble
()
{
SET_OPCODE
(
ADD_REG_RDN
);
ENCODE_RM
;
Get
()
->
rdn
=
rdn
->
Code
();
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t16.h
View file @
612980be
...
...
@@ -128,9 +128,9 @@ namespace SandHook {
Off
GetImmPCOffset
()
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
Off
offset
;
...
...
@@ -152,9 +152,9 @@ namespace SandHook {
void
OnOffsetApply
(
Off
offset
)
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
Condition
condition
;
...
...
@@ -176,9 +176,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
BX_BLX
,
TEST_INST_OPCODE
(
BX_BLX
,
1
)
&&
TEST_INST_OPCODE
(
BX_BLX
,
2
))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -207,9 +207,9 @@ namespace SandHook {
Off
GetImmPCOffset
()
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -233,9 +233,9 @@ namespace SandHook {
void
OnOffsetApply
(
Off
offset
)
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
Off
offset
;
...
...
@@ -251,9 +251,9 @@ namespace SandHook {
DEFINE_IS
(
ADD_IMM_RDN
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterA32
*
rdn
;
...
...
@@ -277,9 +277,9 @@ namespace SandHook {
void
OnOffsetApply
(
Off
offset
)
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterA32
*
rd
;
...
...
@@ -298,9 +298,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
CMP_REG
,
TEST_INST_FIELD
(
opcode_base
,
OPCODE_T16
(
DATA_PROC
))
&&
TEST_INST_FIELD
(
opcode
,
OPCODE_T16
(
CMP_REG
)))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterA32
*
rm
;
...
...
@@ -318,9 +318,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
MOV_REG
,
TEST_INST_FIELD
(
opcode_base
,
OPCODE_T16
(
DATA_PROC
))
&&
TEST_INST_FIELD
(
opcode
,
OPCODE_T16
(
MOV_REG
)))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
bool
PcRelate
()
override
;
...
...
@@ -339,9 +339,9 @@ namespace SandHook {
DEFINE_IS
(
ADD_REG
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterA32
*
rd
;
...
...
@@ -359,9 +359,9 @@ namespace SandHook {
DEFINE_IS
(
CMP_REG_EXT
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
...
...
@@ -378,9 +378,9 @@ namespace SandHook {
DEFINE_IS
(
POP
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterList
registerList
;
...
...
@@ -396,9 +396,9 @@ namespace SandHook {
DEFINE_IS
(
PUSH
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterList
registerList
;
...
...
@@ -417,9 +417,9 @@ namespace SandHook {
bool
PcRelate
()
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterA32
*
rdn
;
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.cpp
View file @
612980be
...
...
@@ -45,13 +45,13 @@ Off T32_B32::GetImmPCOffset() {
return
SignExtend32
(
25
,
COMBINE
(
Si1i2
,
imm21
,
21
)
<<
1
);
}
void
T32_B32
::
Disassemble
r
()
{
void
T32_B32
::
Disassemble
()
{
DECODE_OP
;
x
=
X
(
Get
()
->
X
);
offset
=
GetImmPCOffset
();
}
void
T32_B32
::
Assemble
r
()
{
void
T32_B32
::
Assemble
()
{
SET_OPCODE
(
B32
);
ENCODE_OP
;
Get
()
->
X
=
x
;
...
...
@@ -91,14 +91,14 @@ T32_LDR_UIMM::T32_LDR_UIMM(void *inst) : InstructionT32(inst) {}
T32_LDR_UIMM
::
T32_LDR_UIMM
(
RegisterA32
&
rt
,
RegisterA32
&
rn
,
U32
offset
)
:
rt
(
&
rt
),
rn
(
&
rn
),
offset
(
offset
)
{}
void
T32_LDR_UIMM
::
Disassemble
r
()
{
void
T32_LDR_UIMM
::
Disassemble
()
{
DECODE_RN
(
Reg
);
DECODE_RT
(
Reg
);
INST_ASSERT
(
rn
==
&
PC
);
offset
=
Get
()
->
imm12
;
}
void
T32_LDR_UIMM
::
Assemble
r
()
{
void
T32_LDR_UIMM
::
Assemble
()
{
SET_OPCODE
(
LDR_UIMM
);
ENCODE_RN
;
ENCODE_RT
;
...
...
@@ -131,14 +131,14 @@ void T32_LDR_LIT::OnOffsetApply(Off offset) {
}
}
void
T32_LDR_LIT
::
Disassemble
r
()
{
void
T32_LDR_LIT
::
Disassemble
()
{
DECODE_OP
;
DECODE_RT
(
Reg
);
s
=
S
(
Get
()
->
S
);
offset
=
GetImmPCOffset
();
}
void
T32_LDR_LIT
::
Assemble
r
()
{
void
T32_LDR_LIT
::
Assemble
()
{
SET_OPCODE
(
LDR_LIT
);
ENCODE_OP
;
ENCODE_RT
;
...
...
@@ -161,7 +161,7 @@ T32_MOV_MOVT_IMM::T32_MOV_MOVT_IMM(T32_MOV_MOVT_IMM::OP op, RegisterA32 &rd, U16
rd
(
&
rd
),
imm16
(
imm16
)
{}
void
T32_MOV_MOVT_IMM
::
Disassemble
r
()
{
void
T32_MOV_MOVT_IMM
::
Disassemble
()
{
DECODE_OP
;
DECODE_RD
(
Reg
);
U16
imm4i
=
COMBINE
(
Get
()
->
imm4
,
Get
()
->
i
,
1
);
...
...
@@ -169,7 +169,7 @@ void T32_MOV_MOVT_IMM::Disassembler() {
imm16
=
COMBINE
(
imm4i
,
imm38
,
11
);
}
void
T32_MOV_MOVT_IMM
::
Assemble
r
()
{
void
T32_MOV_MOVT_IMM
::
Assemble
()
{
SET_OPCODE_MULTI
(
MOV_MOVT_IMM
,
1
);
SET_OPCODE_MULTI
(
MOV_MOVT_IMM
,
2
);
ENCODE_OP
;
...
...
@@ -188,7 +188,7 @@ T32_LDR_IMM::T32_LDR_IMM(T32_LDR_IMM::OP op, RegisterA32 &rt, const MemOperand &
rt
(
&
rt
),
operand
(
operand
)
{}
void
T32_LDR_IMM
::
Disassemble
r
()
{
void
T32_LDR_IMM
::
Disassemble
()
{
DECODE_OP
;
DECODE_RT
(
Reg
);
operand
.
rn
=
Reg
(
static_cast
<
U8
>
(
Get
()
->
rn
));
...
...
@@ -204,7 +204,7 @@ void T32_LDR_IMM::Disassembler() {
operand
.
offset
=
Get
()
->
U
==
0
?
-
Get
()
->
imm8
:
Get
()
->
imm8
;
}
void
T32_LDR_IMM
::
Assemble
r
()
{
void
T32_LDR_IMM
::
Assemble
()
{
SET_OPCODE_MULTI
(
LDR_IMM
,
1
);
SET_OPCODE_MULTI
(
LDR_IMM
,
2
);
ENCODE_OP
;
...
...
nativehook/src/main/cpp/archs/arm/arm32/inst/inst_t32.h
View file @
612980be
...
...
@@ -140,9 +140,9 @@ namespace SandHook {
Off
GetImmPCOffset
()
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -159,9 +159,9 @@ namespace SandHook {
DEFINE_IS
(
LDR_UIMM
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterA32
*
rt
;
...
...
@@ -201,9 +201,9 @@ namespace SandHook {
void
OnOffsetApply
(
Off
offset
)
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -227,9 +227,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
MOV_MOVT_IMM
,
TEST_INST_OPCODE
(
MOV_MOVT_IMM
,
1
)
&&
TEST_INST_OPCODE
(
MOV_MOVT_IMM
,
2
)
&&
(
TEST_INST_FIELD
(
op
,
MOV
)
||
TEST_INST_FIELD
(
op
,
MOVT
)))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -255,9 +255,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
LDR_IMM
,
TEST_INST_OPCODE
(
LDR_IMM
,
1
)
&&
TEST_INST_OPCODE
(
LDR_IMM
,
2
))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
nativehook/src/main/cpp/archs/arm/arm64/decoder/decoder_arm64.cpp
View file @
612980be
...
...
@@ -50,7 +50,7 @@ void Arm64Decoder::Disassembler(void *codeStart, Addr codeLen, InstVisitor &visi
if
(
unit
==
nullptr
)
{
unit
=
reinterpret_cast
<
BaseUnit
*>
(
new
INST_A64
(
UNKNOW
)(
pc
));
}
reinterpret_cast
<
BaseInst
*>
(
unit
)
->
Disassemble
r
();
reinterpret_cast
<
BaseInst
*>
(
unit
)
->
Disassemble
();
if
(
!
visitor
.
Visit
(
unit
,
pc
))
{
break
;
}
...
...
nativehook/src/main/cpp/archs/arm/arm64/inst/inst_arm64.cpp
View file @
612980be
This diff is collapsed.
Click to expand it.
nativehook/src/main/cpp/archs/arm/arm64/inst/inst_arm64.h
View file @
612980be
...
...
@@ -217,9 +217,9 @@ namespace SandHook {
Addr
GetImmPCOffsetTarget
()
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -254,9 +254,9 @@ namespace SandHook {
DEFINE_IS
(
MOV_WIDE
)
void
Assemble
r
()
override
;
void
Assemble
()
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
public
:
//can be 16/32/64/128
...
...
@@ -297,9 +297,9 @@ namespace SandHook {
void
OnOffsetApply
(
Off
offset
)
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
...
...
@@ -328,9 +328,9 @@ namespace SandHook {
Off
GetImmPCOffset
()
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -354,9 +354,9 @@ namespace SandHook {
void
OnOffsetApply
(
Off
offset
)
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
Condition
condition
;
...
...
@@ -385,9 +385,9 @@ namespace SandHook {
Off
GetImmPCOffset
()
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -419,9 +419,9 @@ namespace SandHook {
void
OnOffsetApply
(
Off
offset
)
override
;
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -445,9 +445,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
BR_BLR_RET
,
TEST_INST_OPCODE
(
BR_BLR_RET
,
1
)
&&
TEST_INST_OPCODE
(
BR_BLR_RET
,
2
)
&&
TEST_INST_OPCODE
(
BR_BLR_RET
,
3
))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -496,9 +496,9 @@ namespace SandHook {
DEFINE_IS
(
STR_IMM
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
};
...
...
@@ -512,9 +512,9 @@ namespace SandHook {
DEFINE_IS
(
STR_UIMM
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
};
...
...
@@ -527,9 +527,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
MOV_REG
,
TEST_INST_OPCODE
(
MOV_REG
,
1
)
&&
TEST_INST_OPCODE
(
MOV_REG
,
2
))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
RegisterA64
*
rd
;
...
...
@@ -547,9 +547,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
SUB_EXT_REG
,
TEST_INST_OPCODE
(
SUB_EXT_REG
,
1
)
&&
TEST_INST_OPCODE
(
SUB_EXT_REG
,
2
))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
...
...
@@ -576,9 +576,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
EXCEPTION_GEN
,
TEST_INST_OPCODE
(
EXCEPTION_GEN
,
1
)
&&
TEST_INST_OPCODE
(
EXCEPTION_GEN
,
2
))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -608,9 +608,9 @@ namespace SandHook {
DEFINE_IS
(
LDR_IMM
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
};
...
...
@@ -623,9 +623,9 @@ namespace SandHook {
DEFINE_IS
(
LDR_UIMM
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
};
DEFINE_INST_EXT
(
LDRSW_IMM
,
LDR_IMM
)
{
...
...
@@ -638,9 +638,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
LDRSW_IMM
,
TEST_INST_FIELD
(
opcode
,
OPCODE_A64
(
LDRSW_IMM
))
&&
TEST_INST_FIELD
(
size
,
Size32
))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
};
...
...
@@ -655,9 +655,9 @@ namespace SandHook {
DEFINE_IS_EXT
(
LDRSW_UIMM
,
TEST_INST_FIELD
(
opcode
,
OPCODE_A64
(
LDRSW_UIMM
))
&&
TEST_INST_FIELD
(
size
,
Size32
))
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
};
...
...
@@ -685,9 +685,9 @@ namespace SandHook {
DEFINE_IS
(
STP_LDP
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -721,9 +721,9 @@ namespace SandHook {
DEFINE_IS
(
ADD_SUB_IMM
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
@@ -747,9 +747,9 @@ namespace SandHook {
DEFINE_IS
(
MSR_MRS
)
void
Disassemble
r
()
override
;
void
Disassemble
()
override
;
void
Assemble
r
()
override
;
void
Assemble
()
override
;
public
:
OP
op
;
...
...
nativehook/src/main/cpp/asm/instruction.h
View file @
612980be
...
...
@@ -85,11 +85,11 @@ namespace SandHook {
label
->
AddBind
(
this
);
}
virtual
void
Disassemble
r
()
{
virtual
void
Disassemble
()
{
backup_
=
*
this
->
pc_
;
}
virtual
void
Assemble
r
()
{
virtual
void
Assemble
()
{
*
this
->
pc_
=
backup_
;
}
...
...
nativehook/src/main/cpp/assembler/assembler.cpp
View file @
612980be
...
...
@@ -46,7 +46,7 @@ void CodeContainer::commit() {
(
*
unit
)
->
Set
(
reinterpret_cast
<
Base
*>
(
pcNow
));
}
if
((
*
unit
)
->
UnitType
()
==
UnitInst
)
{
reinterpret_cast
<
BaseInst
*>
(
*
unit
)
->
Assemble
r
();
reinterpret_cast
<
BaseInst
*>
(
*
unit
)
->
Assemble
();
}
pcNow
+=
(
*
unit
)
->
Size
();
}
...
...
nativehook/src/main/cpp/sandhook_native.cpp
View file @
612980be
...
...
@@ -100,7 +100,7 @@ void breakCallback(REG regs[]) {
class
Visitor
:
public
InstVisitor
{
bool
Visit
(
Unit
<
Base
>
*
unit
,
void
*
pc
)
override
{
BaseInst
*
instruction
=
reinterpret_cast
<
BaseInst
*>
(
unit
);
instruction
->
Assemble
r
();
instruction
->
Assemble
();
return
true
;
}
};
...
...
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