Commit 785422da authored by swift_gan's avatar swift_gan Committed by swift_gan

tweak inst

parent a3db525c
...@@ -10,7 +10,6 @@ using namespace SandHook::Asm; ...@@ -10,7 +10,6 @@ using namespace SandHook::Asm;
//PC Rel Inst //PC Rel Inst
A64_INST_PC_REL::A64_INST_PC_REL() {} A64_INST_PC_REL::A64_INST_PC_REL() {}
A64_INST_PC_REL::A64_INST_PC_REL(aarch64_pcrel_insts *inst) : InstructionA64(inst) {} A64_INST_PC_REL::A64_INST_PC_REL(aarch64_pcrel_insts *inst) : InstructionA64(inst) {}
...@@ -36,7 +35,9 @@ ADDR A64_INST_PC_REL::getImmPCOffsetTarget() { ...@@ -36,7 +35,9 @@ ADDR A64_INST_PC_REL::getImmPCOffsetTarget() {
A64_ADR_ADRP::A64_ADR_ADRP() {} A64_ADR_ADRP::A64_ADR_ADRP() {}
A64_ADR_ADRP::A64_ADR_ADRP(aarch64_pcrel_insts *inst) : A64_INST_PC_REL(inst) {} A64_ADR_ADRP::A64_ADR_ADRP(aarch64_pcrel_insts *inst) : A64_INST_PC_REL(inst) {
decode(inst);
}
ADDR A64_ADR_ADRP::getImmPCOffset() { ADDR A64_ADR_ADRP::getImmPCOffset() {
...@@ -56,6 +57,19 @@ int A64_ADR_ADRP::getImm() { ...@@ -56,6 +57,19 @@ int A64_ADR_ADRP::getImm() {
return getImmPCRel(); return getImmPCRel();
} }
A64_ADR_ADRP::A64_ADR_ADRP(A64_ADR_ADRP::OP op, RegisterA64 *rd, int imme) : op(op), rd(rd),
imme(imme) {
assembler();
}
void A64_ADR_ADRP::decode(aarch64_pcrel_insts *decode) {
}
void A64_ADR_ADRP::assembler() {
}
//Mov Wide //Mov Wide
...@@ -65,7 +79,7 @@ A64_MOV_WIDE::A64_MOV_WIDE(aarch64_mov_wide *inst) : InstructionA64(inst) { ...@@ -65,7 +79,7 @@ A64_MOV_WIDE::A64_MOV_WIDE(aarch64_mov_wide *inst) : InstructionA64(inst) {
decode(inst); decode(inst);
} }
A64_MOV_WIDE::A64_MOV_WIDE(A64_MOV_WIDE::MOV_WideOp op,RegisterA64* rd, U16 imme, U8 shift) A64_MOV_WIDE::A64_MOV_WIDE(A64_MOV_WIDE::OP op,RegisterA64* rd, U16 imme, U8 shift)
: shift(shift), op(op), imme(imme), rd(rd) { : shift(shift), op(op), imme(imme), rd(rd) {
assembler(); assembler();
} }
...@@ -82,10 +96,18 @@ void A64_MOV_WIDE::assembler() { ...@@ -82,10 +96,18 @@ void A64_MOV_WIDE::assembler() {
void A64_MOV_WIDE::decode(aarch64_mov_wide *inst) { void A64_MOV_WIDE::decode(aarch64_mov_wide *inst) {
imme = static_cast<U16>(inst->imm16); imme = static_cast<U16>(inst->imm16);
shift = static_cast<U8>(inst->hw * 16); shift = static_cast<U8>(inst->hw * 16);
op = static_cast<MOV_WideOp>(inst->opc); op = static_cast<OP>(inst->opc);
if (inst->sf == 0) { if (inst->sf == 0) {
rd = XRegister::get(static_cast<U8>(inst->rd)); rd = XRegister::get(static_cast<U8>(inst->rd));
} else { } else {
rd = WRegister::get(static_cast<U8>(inst->rd)); rd = WRegister::get(static_cast<U8>(inst->rd));
} }
} }
//B BL
A64_B_BL::A64_B_BL() {}
A64_B_BL::A64_B_BL(aarch64_b_bl *inst) : InstructionA64(inst) {}
...@@ -46,6 +46,8 @@ namespace SandHook { ...@@ -46,6 +46,8 @@ namespace SandHook {
}; };
class A64_INST_PC_REL : public InstructionA64<aarch64_pcrel_insts> { class A64_INST_PC_REL : public InstructionA64<aarch64_pcrel_insts> {
public: public:
...@@ -61,15 +63,28 @@ namespace SandHook { ...@@ -61,15 +63,28 @@ namespace SandHook {
}; };
class A64_ADR_ADRP : public A64_INST_PC_REL { class A64_ADR_ADRP : public A64_INST_PC_REL {
public: public:
enum OP {
ADR = 0b0,
ADRP = 0b1,
};
A64_ADR_ADRP(); A64_ADR_ADRP();
A64_ADR_ADRP(aarch64_pcrel_insts *inst); A64_ADR_ADRP(aarch64_pcrel_insts *inst);
A64_ADR_ADRP(OP op, RegisterA64 *rd, int imme);
inline U32 instCode() override {
return isADRP() ? PCRelAddressingOp::ADRP : PCRelAddressingOp::ADR;
}
inline bool isADRP() { inline bool isADRP() {
return get()->op == 1; return get()->op == OP::ADRP;
} }
ADDR getImmPCOffset(); ADDR getImmPCOffset();
...@@ -78,12 +93,22 @@ namespace SandHook { ...@@ -78,12 +93,22 @@ namespace SandHook {
int getImm(); int getImm();
void decode(aarch64_pcrel_insts *decode) override;
void assembler() override;
private:
OP op;
RegisterA64* rd;
int imme;
}; };
class A64_MOV_WIDE : public InstructionA64<aarch64_mov_wide> { class A64_MOV_WIDE : public InstructionA64<aarch64_mov_wide> {
public: public:
enum MOV_WideOp { enum OP {
// Move and keep. // Move and keep.
MOV_WideOp_K = 0b00, MOV_WideOp_K = 0b00,
// Move with zero. // Move with zero.
...@@ -96,7 +121,20 @@ namespace SandHook { ...@@ -96,7 +121,20 @@ namespace SandHook {
A64_MOV_WIDE(aarch64_mov_wide *inst); A64_MOV_WIDE(aarch64_mov_wide *inst);
A64_MOV_WIDE(A64_MOV_WIDE::MOV_WideOp op, RegisterA64* rd, U16 imme, U8 shift); A64_MOV_WIDE(A64_MOV_WIDE::OP op, RegisterA64* rd, U16 imme, U8 shift);
inline U32 instCode() override {
switch (op) {
case MOV_WideOp_K:
return MOVK;
case MOV_WideOp_N:
return MOVN;
case MOV_WideOp_Z:
return MOVZ;
default:
return 0;
}
}
void assembler() override; void assembler() override;
...@@ -107,7 +145,7 @@ namespace SandHook { ...@@ -107,7 +145,7 @@ namespace SandHook {
return shift; return shift;
} }
inline MOV_WideOp getOpt() { inline OP getOpt() {
return op; return op;
} }
...@@ -123,11 +161,34 @@ namespace SandHook { ...@@ -123,11 +161,34 @@ namespace SandHook {
//can be 16/32/64/128 //can be 16/32/64/128
//hw = shift / 16 //hw = shift / 16
U8 shift; U8 shift;
MOV_WideOp op; OP op;
U16 imme; U16 imme;
RegisterA64* rd; RegisterA64* rd;
}; };
class A64_B_BL : public InstructionA64<aarch64_b_bl> {
public:
enum OP {
B = 0b0,
BL = 0b1
};
A64_B_BL();
A64_B_BL(aarch64_b_bl *inst);
inline U32 instCode() {
return op == B ? UnconditionalBranchOp::B : UnconditionalBranchOp ::BL;
};
private:
OP op;
U32 imme;
};
} }
} }
......
//
// Created by swift on 2019/5/8.
//
#ifndef SANDHOOK_NH_INST_CODE_ARM64_H
#define SANDHOOK_NH_INST_CODE_ARM64_H
#include "inst_struct_aarch64.h"
// Generic fields.
enum GenericInstrField {
SixtyFourBits = 0x80000000,
ThirtyTwoBits = 0x00000000,
FPTypeMask = 0x00C00000,
FP16 = 0x00C00000,
FP32 = 0x00000000,
FP64 = 0x00400000
};
enum PCRelAddressingOp {
PCRelAddressingFixed = 0x10000000,
PCRelAddressingFMask = 0x1F000000,
PCRelAddressingMask = 0x9F000000,
ADR = PCRelAddressingFixed | 0x00000000,
ADRP = PCRelAddressingFixed | 0x80000000
};
// Move wide immediate.
enum MoveWideImmediateOp {
MoveWideImmediateFixed = 0x12800000,
MoveWideImmediateFMask = 0x1F800000,
MoveWideImmediateMask = 0xFF800000,
MOVN = 0x00000000,
MOVZ = 0x40000000,
MOVK = 0x60000000,
MOVN_w = MoveWideImmediateFixed | MOVN,
MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
MOVZ_w = MoveWideImmediateFixed | MOVZ,
MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
MOVK_w = MoveWideImmediateFixed | MOVK,
MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
};
// Unconditional branch.
enum UnconditionalBranchOp {
UnconditionalBranchFixed = 0x14000000,
UnconditionalBranchFMask = 0x7C000000,
UnconditionalBranchMask = 0xFC000000,
B = UnconditionalBranchFixed | 0x00000000,
BL = UnconditionalBranchFixed | 0x80000000
};
#endif //SANDHOOK_NH_INST_CODE_ARM64_H
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
#include "../../../asm/instruction.h" #include "../../../asm/instruction.h"
#include "inst_code_arm64.h"
enum InstructionFields { enum InstructionFields {
...@@ -28,44 +29,6 @@ enum InstructionFields { ...@@ -28,44 +29,6 @@ enum InstructionFields {
}; };
// Generic fields.
enum GenericInstrField {
SixtyFourBits = 0x80000000,
ThirtyTwoBits = 0x00000000,
FPTypeMask = 0x00C00000,
FP16 = 0x00C00000,
FP32 = 0x00000000,
FP64 = 0x00400000
};
enum PCRelAddressingOp {
PCRelAddressingFixed = 0x10000000,
PCRelAddressingFMask = 0x1F000000,
PCRelAddressingMask = 0x9F000000,
ADR = PCRelAddressingFixed | 0x00000000,
ADRP = PCRelAddressingFixed | 0x80000000
};
// Move wide immediate.
enum MoveWideImmediateOp {
MoveWideImmediateFixed = 0x12800000,
MoveWideImmediateFMask = 0x1F800000,
MoveWideImmediateMask = 0xFF800000,
MOVN = 0x00000000,
MOVZ = 0x40000000,
MOVK = 0x60000000,
MOVN_w = MoveWideImmediateFixed | MOVN,
MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
MOVZ_w = MoveWideImmediateFixed | MOVZ,
MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
MOVK_w = MoveWideImmediateFixed | MOVK,
MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
};
enum ImmBranchType { enum ImmBranchType {
UnknownBranchType = 0, UnknownBranchType = 0,
CondBranchType = 1, CondBranchType = 1,
...@@ -97,4 +60,11 @@ struct aarch64_mov_wide { ...@@ -97,4 +60,11 @@ struct aarch64_mov_wide {
InstA64 rd:5; InstA64 rd:5;
}; };
struct aarch64_b_bl {
InstA64 op:1;
InstA64 opc:5;
InstA64 imm26:26;
};
#endif //SANDHOOK_NH_INST_AARCH64_H #endif //SANDHOOK_NH_INST_AARCH64_H
...@@ -18,5 +18,11 @@ AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS) ...@@ -18,5 +18,11 @@ AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS)
WRegister WSP(RegisterA64::kSPRegInternalCode); WRegister WSP(RegisterA64::kSPRegInternalCode);
XRegister SP(RegisterA64::kSPRegInternalCode); XRegister SP(RegisterA64::kSPRegInternalCode);
XRegister IP0 = X16;
XRegister IP1 = X17;
XRegister LR = X30;
//zero reg
XRegister XZR = X31;
WRegister WZR = W31;
#endif //SANDHOOK_NH_REGISTER_LIST_A64_H #endif //SANDHOOK_NH_REGISTER_LIST_A64_H
...@@ -87,6 +87,10 @@ namespace SandHook { ...@@ -87,6 +87,10 @@ namespace SandHook {
return unkownArch; return unkownArch;
} }
virtual U32 instCode() {
return 0;
};
virtual bool pcRelate() { virtual bool pcRelate() {
return false; return false;
} }
......
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