Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Contribute to GitLab
Sign in / Register
Toggle navigation
S
SandHook
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Administrator
SandHook
Commits
852ee689
Commit
852ee689
authored
May 08, 2019
by
swift_gan
Committed by
swift_gan
May 08, 2019
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
tweak code
parent
83751ac9
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
47 additions
and
23 deletions
+47
-23
inst_arm64.cpp
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.cpp
+10
-9
inst_arm64.h
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.h
+26
-8
inst_struct_aarch64.h
...ehook/src/main/cpp/archs/arm64/inst/inst_struct_aarch64.h
+11
-6
No files found.
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.cpp
View file @
852ee689
...
@@ -5,8 +5,9 @@
...
@@ -5,8 +5,9 @@
#include "inst_arm64.h"
#include "inst_arm64.h"
#include "../register/register_a64.h"
#include "../register/register_a64.h"
using
namespace
SandHook
::
Asm
;
#define SET_OPCODE(X) get()->opcode = OPCODE_A64(X)
using
namespace
SandHook
::
Asm
;
template
<
typename
InstStruct
>
template
<
typename
InstStruct
>
U8
InstructionA64
<
InstStruct
>::
size
()
{
U8
InstructionA64
<
InstStruct
>::
size
()
{
...
@@ -31,7 +32,7 @@ ADDR A64_INST_PC_REL<Inst>::getImmPCOffsetTarget() {
...
@@ -31,7 +32,7 @@ ADDR A64_INST_PC_REL<Inst>::getImmPCOffsetTarget() {
A64_ADR_ADRP
::
A64_ADR_ADRP
()
{}
A64_ADR_ADRP
::
A64_ADR_ADRP
()
{}
A64_ADR_ADRP
::
A64_ADR_ADRP
(
aarch64_adr_adrp
*
inst
)
:
A64_INST_PC_REL
(
inst
)
{
A64_ADR_ADRP
::
A64_ADR_ADRP
(
STRUCT_A64
(
ADR_ADRP
)
*
inst
)
:
A64_INST_PC_REL
(
inst
)
{
decode
(
inst
);
decode
(
inst
);
}
}
...
@@ -59,12 +60,12 @@ A64_ADR_ADRP::A64_ADR_ADRP(A64_ADR_ADRP::OP op, RegisterA64 *rd, int imme) : op(
...
@@ -59,12 +60,12 @@ A64_ADR_ADRP::A64_ADR_ADRP(A64_ADR_ADRP::OP op, RegisterA64 *rd, int imme) : op(
assembler
();
assembler
();
}
}
void
A64_ADR_ADRP
::
decode
(
aarch64_adr_adrp
*
decode
)
{
void
A64_ADR_ADRP
::
decode
(
STRUCT_A64
(
ADR_ADRP
)
*
decode
)
{
}
}
void
A64_ADR_ADRP
::
assembler
()
{
void
A64_ADR_ADRP
::
assembler
()
{
SET_OPCODE
(
ADR_ADRP
);
}
}
...
@@ -82,7 +83,7 @@ A64_MOV_WIDE::A64_MOV_WIDE(A64_MOV_WIDE::OP op,RegisterA64* rd, U16 imme, U8 shi
...
@@ -82,7 +83,7 @@ A64_MOV_WIDE::A64_MOV_WIDE(A64_MOV_WIDE::OP op,RegisterA64* rd, U16 imme, U8 shi
}
}
void
A64_MOV_WIDE
::
assembler
()
{
void
A64_MOV_WIDE
::
assembler
()
{
get
()
->
opcode
=
MOV_WIDE_OPCODE
;
SET_OPCODE
(
MOV_WIDE
)
;
get
()
->
imm16
=
imme
;
get
()
->
imm16
=
imme
;
get
()
->
hw
=
static_cast
<
InstA64
>
(
shift
/
16
);
get
()
->
hw
=
static_cast
<
InstA64
>
(
shift
/
16
);
get
()
->
opc
=
op
;
get
()
->
opc
=
op
;
...
@@ -125,7 +126,7 @@ void A64_B_BL::decode(aarch64_b_bl *inst) {
...
@@ -125,7 +126,7 @@ void A64_B_BL::decode(aarch64_b_bl *inst) {
}
}
void
A64_B_BL
::
assembler
()
{
void
A64_B_BL
::
assembler
()
{
get
()
->
opcode
=
B_BL_OPCODE
;
SET_OPCODE
(
B_BL
)
;
get
()
->
op
=
op
;
get
()
->
op
=
op
;
get
()
->
imm26
=
TruncateToUint26
(
offset
);
get
()
->
imm26
=
TruncateToUint26
(
offset
);
}
}
...
@@ -161,7 +162,7 @@ void A64_CBZ_CBNZ::decode(aarch64_cbz_cbnz *inst) {
...
@@ -161,7 +162,7 @@ void A64_CBZ_CBNZ::decode(aarch64_cbz_cbnz *inst) {
}
}
void
A64_CBZ_CBNZ
::
assembler
()
{
void
A64_CBZ_CBNZ
::
assembler
()
{
get
()
->
opcode
=
CBZ_CBNZ_OPCODE
;
SET_OPCODE
(
CBZ_CBNZ
)
;
get
()
->
op
=
op
;
get
()
->
op
=
op
;
get
()
->
rt
=
rt
->
getCode
();
get
()
->
rt
=
rt
->
getCode
();
get
()
->
sf
=
rt
->
is64Bit
()
?
1
:
0
;
get
()
->
sf
=
rt
->
is64Bit
()
?
1
:
0
;
...
@@ -191,7 +192,7 @@ void A64_B_COND::decode(aarch64_b_cond *inst) {
...
@@ -191,7 +192,7 @@ void A64_B_COND::decode(aarch64_b_cond *inst) {
}
}
void
A64_B_COND
::
assembler
()
{
void
A64_B_COND
::
assembler
()
{
get
()
->
opcode
=
CBZ_B_COND_OPCODE
;
SET_OPCODE
(
B_COND
)
;
get
()
->
cond
=
condition
;
get
()
->
cond
=
condition
;
get
()
->
imm19
=
TruncateToUint19
(
offset
);
get
()
->
imm19
=
TruncateToUint19
(
offset
);
}
}
...
@@ -228,7 +229,7 @@ void A64_TBZ_TBNZ::decode(aarch64_tbz_tbnz *inst) {
...
@@ -228,7 +229,7 @@ void A64_TBZ_TBNZ::decode(aarch64_tbz_tbnz *inst) {
}
}
void
A64_TBZ_TBNZ
::
assembler
()
{
void
A64_TBZ_TBNZ
::
assembler
()
{
get
()
->
opcode
=
TBZ_TBNZ_OPCODE
;
SET_OPCODE
(
TBZ_TBNZ
)
;
get
()
->
op
=
op
;
get
()
->
op
=
op
;
get
()
->
b5
=
rt
->
is64Bit
()
?
1
:
0
;
get
()
->
b5
=
rt
->
is64Bit
()
?
1
:
0
;
get
()
->
rt
=
rt
->
getCode
();
get
()
->
rt
=
rt
->
getCode
();
...
...
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.h
View file @
852ee689
...
@@ -12,6 +12,22 @@
...
@@ -12,6 +12,22 @@
#include "../register/register_a64.h"
#include "../register/register_a64.h"
#include "../../../../../../../hooklib/src/main/cpp/includes/inst.h"
#include "../../../../../../../hooklib/src/main/cpp/includes/inst.h"
#define INST_A64(X) A64_##X
#define IS_OPCODE(RAW,OP) INST_A64(OP)::is(RAW);
#define DEFINE_IS(X) \
inline static bool is(InstA64& inst) { \
union { \
InstA64 raw; \
STRUCT_A64(X) inst; \
} inst_test; \
inst_test.raw = inst; \
return inst_test.inst.opcode == OPCODE_A64(X); \
}
namespace
SandHook
{
namespace
SandHook
{
namespace
Asm
{
namespace
Asm
{
...
@@ -66,7 +82,7 @@ namespace SandHook {
...
@@ -66,7 +82,7 @@ namespace SandHook {
class
A64_ADR_ADRP
:
public
A64_INST_PC_REL
<
aarch64_adr_adrp
>
{
class
INST_A64
(
ADR_ADRP
)
:
public
A64_INST_PC_REL
<
STRUCT_A64
(
ADR_ADRP
)
>
{
public
:
public
:
enum
OP
{
enum
OP
{
...
@@ -76,10 +92,12 @@ namespace SandHook {
...
@@ -76,10 +92,12 @@ namespace SandHook {
A64_ADR_ADRP
();
A64_ADR_ADRP
();
A64_ADR_ADRP
(
aarch64_adr_adrp
*
inst
);
A64_ADR_ADRP
(
STRUCT_A64
(
ADR_ADRP
)
*
inst
);
A64_ADR_ADRP
(
OP
op
,
RegisterA64
*
rd
,
int
imme
);
A64_ADR_ADRP
(
OP
op
,
RegisterA64
*
rd
,
int
imme
);
DEFINE_IS
(
ADR_ADRP
)
U32
instCode
()
override
{
U32
instCode
()
override
{
return
isADRP
()
?
PCRelAddressingOp
::
ADRP
:
PCRelAddressingOp
::
ADR
;
return
isADRP
()
?
PCRelAddressingOp
::
ADRP
:
PCRelAddressingOp
::
ADR
;
}
}
...
@@ -94,7 +112,7 @@ namespace SandHook {
...
@@ -94,7 +112,7 @@ namespace SandHook {
int
getImm
();
int
getImm
();
void
decode
(
aarch64_adr_adrp
*
decode
)
override
;
void
decode
(
STRUCT_A64
(
ADR_ADRP
)
*
decode
)
override
;
void
assembler
()
override
;
void
assembler
()
override
;
...
@@ -106,7 +124,7 @@ namespace SandHook {
...
@@ -106,7 +124,7 @@ namespace SandHook {
class
A64_MOV_WIDE
:
public
InstructionA64
<
aarch64_mov_wide
>
{
class
INST_A64
(
MOV_WIDE
)
:
public
InstructionA64
<
aarch64_mov_wide
>
{
public
:
public
:
enum
OP
{
enum
OP
{
...
@@ -169,7 +187,7 @@ namespace SandHook {
...
@@ -169,7 +187,7 @@ namespace SandHook {
class
A64_B_BL
:
public
A64_INST_PC_REL
<
aarch64_b_bl
>
{
class
INST_A64
(
B_BL
)
:
public
A64_INST_PC_REL
<
aarch64_b_bl
>
{
public
:
public
:
enum
OP
{
enum
OP
{
...
@@ -208,7 +226,7 @@ namespace SandHook {
...
@@ -208,7 +226,7 @@ namespace SandHook {
};
};
class
A64_CBZ_CBNZ
:
public
A64_INST_PC_REL
<
aarch64_cbz_cbnz
>
{
class
INST_A64
(
CBZ_CBNZ
)
:
public
A64_INST_PC_REL
<
aarch64_cbz_cbnz
>
{
public
:
public
:
enum
OP
{
enum
OP
{
...
@@ -239,7 +257,7 @@ namespace SandHook {
...
@@ -239,7 +257,7 @@ namespace SandHook {
};
};
class
A64_B_COND
:
public
A64_INST_PC_REL
<
aarch64_b_cond
>
{
class
INST_A64
(
B_COND
)
:
public
A64_INST_PC_REL
<
aarch64_b_cond
>
{
public
:
public
:
A64_B_COND
();
A64_B_COND
();
...
@@ -263,7 +281,7 @@ namespace SandHook {
...
@@ -263,7 +281,7 @@ namespace SandHook {
};
};
class
A64_TBZ_TBNZ
:
public
A64_INST_PC_REL
<
aarch64_tbz_tbnz
>
{
class
INST_A64
(
TBZ_TBNZ
)
:
public
A64_INST_PC_REL
<
aarch64_tbz_tbnz
>
{
public
:
public
:
enum
OP
{
enum
OP
{
...
...
nativehook/src/main/cpp/archs/arm64/inst/inst_struct_aarch64.h
View file @
852ee689
...
@@ -9,6 +9,10 @@
...
@@ -9,6 +9,10 @@
#include "../../../asm/instruction.h"
#include "../../../asm/instruction.h"
#include "inst_code_arm64.h"
#include "inst_code_arm64.h"
#define STRUCT_A64(X) A64_STRUCT_##X
#define OPCODE_A64(X) A64_OPCODE_##X
#define DEFINE_OPCODE(X, V) const U32 OPCODE_A64(X) = V;
enum
InstructionFields
{
enum
InstructionFields
{
// Registers.
// Registers.
...
@@ -63,7 +67,8 @@ enum Condition {
...
@@ -63,7 +67,8 @@ enum Condition {
#define IMM_LO_W 2
#define IMM_LO_W 2
#define IMM_HI_W 19
#define IMM_HI_W 19
struct
aarch64_adr_adrp
{
DEFINE_OPCODE
(
ADR_ADRP
,
0
b10000
)
struct
STRUCT_A64
(
ADR_ADRP
)
{
InstA64
op
:
1
;
InstA64
op
:
1
;
InstA64
immlo
:
IMM_LO_W
;
InstA64
immlo
:
IMM_LO_W
;
InstA64
opcode
:
5
;
InstA64
opcode
:
5
;
...
@@ -72,7 +77,7 @@ struct aarch64_adr_adrp {
...
@@ -72,7 +77,7 @@ struct aarch64_adr_adrp {
};
};
#define MOV_WIDE_OPCODE 0b100101
DEFINE_OPCODE
(
MOV_WIDE
,
0
b100101
)
struct
aarch64_mov_wide
{
struct
aarch64_mov_wide
{
InstA64
sf
:
1
;
InstA64
sf
:
1
;
InstA64
opc
:
2
;
InstA64
opc
:
2
;
...
@@ -82,14 +87,14 @@ struct aarch64_mov_wide {
...
@@ -82,14 +87,14 @@ struct aarch64_mov_wide {
InstA64
rd
:
5
;
InstA64
rd
:
5
;
};
};
#define B_BL_OPCODE 0b00101
DEFINE_OPCODE
(
B_BL
,
0
b00101
)
struct
aarch64_b_bl
{
struct
aarch64_b_bl
{
InstA64
op
:
1
;
InstA64
op
:
1
;
InstA64
opcode
:
5
;
InstA64
opcode
:
5
;
InstA64
imm26
:
26
;
InstA64
imm26
:
26
;
};
};
#define CBZ_CBNZ_OPCODE 0b011010
DEFINE_OPCODE
(
CBZ_CBNZ
,
0
b011010
)
struct
aarch64_cbz_cbnz
{
struct
aarch64_cbz_cbnz
{
InstA64
sf
:
1
;
InstA64
sf
:
1
;
InstA64
opcode
:
6
;
InstA64
opcode
:
6
;
...
@@ -98,7 +103,7 @@ struct aarch64_cbz_cbnz {
...
@@ -98,7 +103,7 @@ struct aarch64_cbz_cbnz {
InstA64
rt
:
5
;
InstA64
rt
:
5
;
};
};
#define CBZ_B_COND_OPCODE 0b01010100
DEFINE_OPCODE
(
B_COND
,
0
b01010100
)
struct
aarch64_b_cond
{
struct
aarch64_b_cond
{
InstA64
opcode
:
8
;
InstA64
opcode
:
8
;
InstA64
imm19
:
19
;
InstA64
imm19
:
19
;
...
@@ -107,7 +112,7 @@ struct aarch64_b_cond {
...
@@ -107,7 +112,7 @@ struct aarch64_b_cond {
};
};
#define TBZ_TBNZ_OPCODE 0b011011
DEFINE_OPCODE
(
TBZ_TBNZ
,
0
b011011
)
struct
aarch64_tbz_tbnz
{
struct
aarch64_tbz_tbnz
{
InstA64
b5
:
1
;
InstA64
b5
:
1
;
InstA64
opcode
:
6
;
InstA64
opcode
:
6
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment