Commit 852ee689 authored by swift_gan's avatar swift_gan Committed by swift_gan

tweak code

parent 83751ac9
......@@ -5,8 +5,9 @@
#include "inst_arm64.h"
#include "../register/register_a64.h"
using namespace SandHook::Asm;
#define SET_OPCODE(X) get()->opcode = OPCODE_A64(X)
using namespace SandHook::Asm;
template<typename InstStruct>
U8 InstructionA64<InstStruct>::size() {
......@@ -31,7 +32,7 @@ ADDR A64_INST_PC_REL<Inst>::getImmPCOffsetTarget() {
A64_ADR_ADRP::A64_ADR_ADRP() {}
A64_ADR_ADRP::A64_ADR_ADRP(aarch64_adr_adrp *inst) : A64_INST_PC_REL(inst) {
A64_ADR_ADRP::A64_ADR_ADRP(STRUCT_A64(ADR_ADRP) *inst) : A64_INST_PC_REL(inst) {
decode(inst);
}
......@@ -59,12 +60,12 @@ A64_ADR_ADRP::A64_ADR_ADRP(A64_ADR_ADRP::OP op, RegisterA64 *rd, int imme) : op(
assembler();
}
void A64_ADR_ADRP::decode(aarch64_adr_adrp *decode) {
void A64_ADR_ADRP::decode(STRUCT_A64(ADR_ADRP) *decode) {
}
void A64_ADR_ADRP::assembler() {
SET_OPCODE(ADR_ADRP);
}
......@@ -82,7 +83,7 @@ A64_MOV_WIDE::A64_MOV_WIDE(A64_MOV_WIDE::OP op,RegisterA64* rd, U16 imme, U8 shi
}
void A64_MOV_WIDE::assembler() {
get()->opcode = MOV_WIDE_OPCODE;
SET_OPCODE(MOV_WIDE);
get()->imm16 = imme;
get()->hw = static_cast<InstA64>(shift / 16);
get()->opc = op;
......@@ -125,7 +126,7 @@ void A64_B_BL::decode(aarch64_b_bl *inst) {
}
void A64_B_BL::assembler() {
get()->opcode = B_BL_OPCODE;
SET_OPCODE(B_BL);
get()->op = op;
get()->imm26 = TruncateToUint26(offset);
}
......@@ -161,7 +162,7 @@ void A64_CBZ_CBNZ::decode(aarch64_cbz_cbnz *inst) {
}
void A64_CBZ_CBNZ::assembler() {
get()->opcode = CBZ_CBNZ_OPCODE;
SET_OPCODE(CBZ_CBNZ);
get()->op = op;
get()->rt = rt->getCode();
get()->sf = rt->is64Bit() ? 1 : 0;
......@@ -191,7 +192,7 @@ void A64_B_COND::decode(aarch64_b_cond *inst) {
}
void A64_B_COND::assembler() {
get()->opcode = CBZ_B_COND_OPCODE;
SET_OPCODE(B_COND);
get()->cond = condition;
get()->imm19 = TruncateToUint19(offset);
}
......@@ -228,7 +229,7 @@ void A64_TBZ_TBNZ::decode(aarch64_tbz_tbnz *inst) {
}
void A64_TBZ_TBNZ::assembler() {
get()->opcode = TBZ_TBNZ_OPCODE;
SET_OPCODE(TBZ_TBNZ);
get()->op = op;
get()->b5 = rt->is64Bit() ? 1 : 0;
get()->rt = rt->getCode();
......
......@@ -12,6 +12,22 @@
#include "../register/register_a64.h"
#include "../../../../../../../hooklib/src/main/cpp/includes/inst.h"
#define INST_A64(X) A64_##X
#define IS_OPCODE(RAW,OP) INST_A64(OP)::is(RAW);
#define DEFINE_IS(X) \
inline static bool is(InstA64& inst) { \
union { \
InstA64 raw; \
STRUCT_A64(X) inst; \
} inst_test; \
inst_test.raw = inst; \
return inst_test.inst.opcode == OPCODE_A64(X); \
}
namespace SandHook {
namespace Asm {
......@@ -66,7 +82,7 @@ namespace SandHook {
class A64_ADR_ADRP : public A64_INST_PC_REL<aarch64_adr_adrp> {
class INST_A64(ADR_ADRP) : public A64_INST_PC_REL<STRUCT_A64(ADR_ADRP)> {
public:
enum OP {
......@@ -76,10 +92,12 @@ namespace SandHook {
A64_ADR_ADRP();
A64_ADR_ADRP(aarch64_adr_adrp *inst);
A64_ADR_ADRP(STRUCT_A64(ADR_ADRP) *inst);
A64_ADR_ADRP(OP op, RegisterA64 *rd, int imme);
DEFINE_IS(ADR_ADRP)
U32 instCode() override {
return isADRP() ? PCRelAddressingOp::ADRP : PCRelAddressingOp::ADR;
}
......@@ -94,7 +112,7 @@ namespace SandHook {
int getImm();
void decode(aarch64_adr_adrp *decode) override;
void decode(STRUCT_A64(ADR_ADRP) *decode) override;
void assembler() override;
......@@ -106,7 +124,7 @@ namespace SandHook {
class A64_MOV_WIDE : public InstructionA64<aarch64_mov_wide> {
class INST_A64(MOV_WIDE) : public InstructionA64<aarch64_mov_wide> {
public:
enum OP {
......@@ -169,7 +187,7 @@ namespace SandHook {
class A64_B_BL : public A64_INST_PC_REL<aarch64_b_bl> {
class INST_A64(B_BL) : public A64_INST_PC_REL<aarch64_b_bl> {
public:
enum OP {
......@@ -208,7 +226,7 @@ namespace SandHook {
};
class A64_CBZ_CBNZ : public A64_INST_PC_REL<aarch64_cbz_cbnz> {
class INST_A64(CBZ_CBNZ) : public A64_INST_PC_REL<aarch64_cbz_cbnz> {
public:
enum OP {
......@@ -239,7 +257,7 @@ namespace SandHook {
};
class A64_B_COND : public A64_INST_PC_REL<aarch64_b_cond> {
class INST_A64(B_COND) : public A64_INST_PC_REL<aarch64_b_cond> {
public:
A64_B_COND();
......@@ -263,7 +281,7 @@ namespace SandHook {
};
class A64_TBZ_TBNZ : public A64_INST_PC_REL<aarch64_tbz_tbnz> {
class INST_A64(TBZ_TBNZ) : public A64_INST_PC_REL<aarch64_tbz_tbnz> {
public:
enum OP {
......
......@@ -9,6 +9,10 @@
#include "../../../asm/instruction.h"
#include "inst_code_arm64.h"
#define STRUCT_A64(X) A64_STRUCT_##X
#define OPCODE_A64(X) A64_OPCODE_##X
#define DEFINE_OPCODE(X, V) const U32 OPCODE_A64(X) = V;
enum InstructionFields {
// Registers.
......@@ -63,7 +67,8 @@ enum Condition {
#define IMM_LO_W 2
#define IMM_HI_W 19
struct aarch64_adr_adrp {
DEFINE_OPCODE(ADR_ADRP, 0b10000)
struct STRUCT_A64(ADR_ADRP) {
InstA64 op:1;
InstA64 immlo:IMM_LO_W;
InstA64 opcode:5;
......@@ -72,7 +77,7 @@ struct aarch64_adr_adrp {
};
#define MOV_WIDE_OPCODE 0b100101
DEFINE_OPCODE(MOV_WIDE, 0b100101)
struct aarch64_mov_wide {
InstA64 sf:1;
InstA64 opc:2;
......@@ -82,14 +87,14 @@ struct aarch64_mov_wide {
InstA64 rd:5;
};
#define B_BL_OPCODE 0b00101
DEFINE_OPCODE(B_BL, 0b00101)
struct aarch64_b_bl {
InstA64 op:1;
InstA64 opcode:5;
InstA64 imm26:26;
};
#define CBZ_CBNZ_OPCODE 0b011010
DEFINE_OPCODE(CBZ_CBNZ, 0b011010)
struct aarch64_cbz_cbnz {
InstA64 sf:1;
InstA64 opcode:6;
......@@ -98,7 +103,7 @@ struct aarch64_cbz_cbnz {
InstA64 rt:5;
};
#define CBZ_B_COND_OPCODE 0b01010100
DEFINE_OPCODE(B_COND, 0b01010100)
struct aarch64_b_cond {
InstA64 opcode:8;
InstA64 imm19:19;
......@@ -107,7 +112,7 @@ struct aarch64_b_cond {
};
#define TBZ_TBNZ_OPCODE 0b011011
DEFINE_OPCODE(TBZ_TBNZ, 0b011011)
struct aarch64_tbz_tbnz {
InstA64 b5:1;
InstA64 opcode:6;
......
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