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Administrator
SandHook
Commits
8a5cc3c0
Commit
8a5cc3c0
authored
May 12, 2019
by
swift_gan
Committed by
swift_gan
May 12, 2019
Browse files
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add inst MOV Register
parent
12e606a5
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
86 additions
and
14 deletions
+86
-14
inst_arm64.cpp
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.cpp
+38
-4
inst_arm64.h
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.h
+22
-0
inst_code_arm64.h
nativehook/src/main/cpp/archs/arm64/inst/inst_code_arm64.h
+2
-0
inst_struct_aarch64.h
...ehook/src/main/cpp/archs/arm64/inst/inst_struct_aarch64.h
+24
-10
No files found.
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.cpp
View file @
8a5cc3c0
...
@@ -39,6 +39,11 @@ Addr A64_INST_PC_REL<Inst>::getImmPCOffsetTarget() {
...
@@ -39,6 +39,11 @@ Addr A64_INST_PC_REL<Inst>::getImmPCOffsetTarget() {
return
this
->
getImmPCOffset
()
+
reinterpret_cast
<
Addr
>
(
this
->
getPC
());
return
this
->
getImmPCOffset
()
+
reinterpret_cast
<
Addr
>
(
this
->
getPC
());
}
}
template
<
typename
Inst
>
bool
A64_INST_PC_REL
<
Inst
>::
pcRelate
()
{
return
true
;
}
//ADR ADRP
//ADR ADRP
A64_ADR_ADRP
::
A64_ADR_ADRP
()
{}
A64_ADR_ADRP
::
A64_ADR_ADRP
()
{}
...
@@ -94,7 +99,7 @@ void A64_MOV_WIDE::assembler() {
...
@@ -94,7 +99,7 @@ void A64_MOV_WIDE::assembler() {
get
()
->
imm16
=
imme
;
get
()
->
imm16
=
imme
;
get
()
->
hw
=
static_cast
<
InstA64
>
(
shift
/
16
);
get
()
->
hw
=
static_cast
<
InstA64
>
(
shift
/
16
);
get
()
->
opc
=
op
;
get
()
->
opc
=
op
;
get
()
->
sf
=
rd
->
is
64Bit
()
?
1
:
0
;
get
()
->
sf
=
rd
->
is
X
()
?
1
:
0
;
get
()
->
rd
=
rd
->
getCode
();
get
()
->
rd
=
rd
->
getCode
();
}
}
...
@@ -178,7 +183,7 @@ void A64_CBZ_CBNZ::assembler() {
...
@@ -178,7 +183,7 @@ void A64_CBZ_CBNZ::assembler() {
SET_OPCODE
(
CBZ_CBNZ
);
SET_OPCODE
(
CBZ_CBNZ
);
get
()
->
op
=
op
;
get
()
->
op
=
op
;
get
()
->
rt
=
rt
->
getCode
();
get
()
->
rt
=
rt
->
getCode
();
get
()
->
sf
=
rt
->
is
64Bit
()
?
1
:
0
;
get
()
->
sf
=
rt
->
is
X
()
?
1
:
0
;
get
()
->
imm19
=
TruncateToUint19
(
offset
>>
2
);
get
()
->
imm19
=
TruncateToUint19
(
offset
>>
2
);
}
}
...
@@ -240,7 +245,7 @@ void A64_TBZ_TBNZ::decode(STRUCT_A64(TBZ_TBNZ) *inst) {
...
@@ -240,7 +245,7 @@ void A64_TBZ_TBNZ::decode(STRUCT_A64(TBZ_TBNZ) *inst) {
void
A64_TBZ_TBNZ
::
assembler
()
{
void
A64_TBZ_TBNZ
::
assembler
()
{
SET_OPCODE
(
TBZ_TBNZ
);
SET_OPCODE
(
TBZ_TBNZ
);
get
()
->
op
=
op
;
get
()
->
op
=
op
;
get
()
->
b5
=
rt
->
is
64Bit
()
?
1
:
0
;
get
()
->
b5
=
rt
->
is
X
()
?
1
:
0
;
get
()
->
rt
=
rt
->
getCode
();
get
()
->
rt
=
rt
->
getCode
();
get
()
->
b40
=
static_cast
<
InstA64
>
(
BITS
(
bit
,
sizeof
(
InstA64
)
-
5
,
sizeof
(
InstA64
)));
get
()
->
b40
=
static_cast
<
InstA64
>
(
BITS
(
bit
,
sizeof
(
InstA64
)
-
5
,
sizeof
(
InstA64
)));
get
()
->
imm14
=
TruncateToUint14
(
offset
>>
2
);
get
()
->
imm14
=
TruncateToUint14
(
offset
>>
2
);
...
@@ -424,4 +429,33 @@ void A64_STR_UIMM::assembler() {
...
@@ -424,4 +429,33 @@ void A64_STR_UIMM::assembler() {
return
;
return
;
}
}
get
()
->
imm12
=
operand
.
offset
>>
get
()
->
size
;
get
()
->
imm12
=
operand
.
offset
>>
get
()
->
size
;
}
}
\ No newline at end of file
A64_MOV_REG
::
A64_MOV_REG
()
{}
A64_MOV_REG
::
A64_MOV_REG
(
STRUCT_A64
(
MOV_REG
)
&
inst
)
:
InstructionA64
(
&
inst
)
{
decode
(
&
inst
);
}
A64_MOV_REG
::
A64_MOV_REG
(
RegisterA64
&
rd
,
RegisterA64
&
rm
)
:
rd
(
&
rd
),
rm
(
&
rm
)
{
}
void
A64_MOV_REG
::
decode
(
A64_STRUCT_MOV_REG
*
inst
)
{
if
(
inst
->
sf
==
1
)
{
rd
=
XReg
(
static_cast
<
U8
>
(
inst
->
rd
));
rm
=
XReg
(
static_cast
<
U8
>
(
inst
->
rm
));
}
else
{
rd
=
WReg
(
static_cast
<
U8
>
(
inst
->
rd
));
rm
=
WReg
(
static_cast
<
U8
>
(
inst
->
rm
));
}
}
void
A64_MOV_REG
::
assembler
()
{
SET_OPCODE_MULTI
(
MOV_REG
,
1
);
SET_OPCODE_MULTI
(
MOV_REG
,
2
);
get
()
->
sf
=
rd
->
isX
()
?
1
:
0
;
get
()
->
rd
=
rd
->
getCode
();
get
()
->
rm
=
rm
->
getCode
();
}
nativehook/src/main/cpp/archs/arm64/inst/inst_arm64.h
View file @
8a5cc3c0
...
@@ -181,6 +181,8 @@ namespace SandHook {
...
@@ -181,6 +181,8 @@ namespace SandHook {
virtual
Addr
getImmPCOffsetTarget
();
virtual
Addr
getImmPCOffsetTarget
();
bool
pcRelate
()
override
;
};
};
...
@@ -575,6 +577,26 @@ namespace SandHook {
...
@@ -575,6 +577,26 @@ namespace SandHook {
Off
offset
;
Off
offset
;
};
};
class
INST_A64
(
MOV_REG
)
:
public
InstructionA64
<
STRUCT_A64
(
MOV_REG
)
>
{
public
:
A64_MOV_REG
();
A64_MOV_REG
(
STRUCT_A64
(
MOV_REG
)
&
inst
);
A64_MOV_REG
(
RegisterA64
&
rd
,
RegisterA64
&
rm
);
DEFINE_IS_EXT
(
MOV_REG
,
TEST_INST_OPCODE
(
MOV_REG
,
1
)
&&
TEST_INST_OPCODE
(
MOV_REG
,
2
))
void
decode
(
A64_STRUCT_MOV_REG
*
inst
)
override
;
void
assembler
()
override
;
public
:
RegisterA64
*
rd
;
RegisterA64
*
rm
;
};
}
}
}
}
...
...
nativehook/src/main/cpp/archs/arm64/inst/inst_code_arm64.h
View file @
8a5cc3c0
...
@@ -7,6 +7,8 @@
...
@@ -7,6 +7,8 @@
#include "inst_struct_aarch64.h"
#include "inst_struct_aarch64.h"
// Generic fields.
// Generic fields.
enum
GenericInstrField
{
enum
GenericInstrField
{
SixtyFourBits
=
0x80000000
,
SixtyFourBits
=
0x80000000
,
...
...
nativehook/src/main/cpp/archs/arm64/inst/inst_struct_aarch64.h
View file @
8a5cc3c0
...
@@ -87,6 +87,10 @@ enum Extend {
...
@@ -87,6 +87,10 @@ enum Extend {
SXTX
=
7
SXTX
=
7
};
};
enum
FieldWide
{
WideReg
=
5
,
};
//unknow inst
//unknow inst
DEFINE_STRUCT_A64
(
UNKNOW
)
{
DEFINE_STRUCT_A64
(
UNKNOW
)
{
InstA64
raw
;
InstA64
raw
;
...
@@ -96,7 +100,7 @@ DEFINE_STRUCT_A64(UNKNOW) {
...
@@ -96,7 +100,7 @@ DEFINE_STRUCT_A64(UNKNOW) {
#define IMM_HI_W 19
#define IMM_HI_W 19
DEFINE_OPCODE
(
ADR_ADRP
,
0
b10000
)
DEFINE_OPCODE
(
ADR_ADRP
,
0
b10000
)
struct
STRUCT_A64
(
ADR_ADRP
)
{
struct
STRUCT_A64
(
ADR_ADRP
)
{
InstA64
rd
:
5
;
InstA64
rd
:
WideReg
;
InstA64
immhi
:
IMM_HI_W
;
InstA64
immhi
:
IMM_HI_W
;
InstA64
opcode
:
5
;
InstA64
opcode
:
5
;
InstA64
immlo
:
IMM_LO_W
;
InstA64
immlo
:
IMM_LO_W
;
...
@@ -105,7 +109,7 @@ struct STRUCT_A64(ADR_ADRP) {
...
@@ -105,7 +109,7 @@ struct STRUCT_A64(ADR_ADRP) {
DEFINE_OPCODE
(
MOV_WIDE
,
0
b100101
)
DEFINE_OPCODE
(
MOV_WIDE
,
0
b100101
)
DEFINE_STRUCT_A64
(
MOV_WIDE
)
{
DEFINE_STRUCT_A64
(
MOV_WIDE
)
{
InstA64
rd
:
5
;
InstA64
rd
:
WideReg
;
InstA64
imm16
:
16
;
InstA64
imm16
:
16
;
InstA64
hw
:
2
;
InstA64
hw
:
2
;
InstA64
opcode
:
6
;
InstA64
opcode
:
6
;
...
@@ -113,6 +117,16 @@ DEFINE_STRUCT_A64(MOV_WIDE) {
...
@@ -113,6 +117,16 @@ DEFINE_STRUCT_A64(MOV_WIDE) {
InstA64
sf
:
1
;
InstA64
sf
:
1
;
};
};
DEFINE_OPCODE
(
MOV_REG_1
,
0
b0101010000
)
DEFINE_OPCODE
(
MOV_REG_2
,
0
b00000011111
)
DEFINE_STRUCT_A64
(
MOV_REG
)
{
InstA64
rd
:
WideReg
;
InstA64
opcode2
:
11
;
InstA64
rm
:
WideReg
;
InstA64
opcode1
:
10
;
InstA64
sf
:
1
;
};
DEFINE_OPCODE
(
B_BL
,
0
b00101
)
DEFINE_OPCODE
(
B_BL
,
0
b00101
)
DEFINE_STRUCT_A64
(
B_BL
)
{
DEFINE_STRUCT_A64
(
B_BL
)
{
InstA64
imm26
:
26
;
InstA64
imm26
:
26
;
...
@@ -122,7 +136,7 @@ DEFINE_STRUCT_A64(B_BL) {
...
@@ -122,7 +136,7 @@ DEFINE_STRUCT_A64(B_BL) {
DEFINE_OPCODE
(
CBZ_CBNZ
,
0
b011010
)
DEFINE_OPCODE
(
CBZ_CBNZ
,
0
b011010
)
DEFINE_STRUCT_A64
(
CBZ_CBNZ
)
{
DEFINE_STRUCT_A64
(
CBZ_CBNZ
)
{
InstA64
rt
:
5
;
InstA64
rt
:
WideReg
;
InstA64
imm19
:
19
;
InstA64
imm19
:
19
;
InstA64
op
:
1
;
InstA64
op
:
1
;
InstA64
opcode
:
6
;
InstA64
opcode
:
6
;
...
@@ -139,7 +153,7 @@ DEFINE_STRUCT_A64(B_COND) {
...
@@ -139,7 +153,7 @@ DEFINE_STRUCT_A64(B_COND) {
DEFINE_OPCODE
(
TBZ_TBNZ
,
0
b011011
)
DEFINE_OPCODE
(
TBZ_TBNZ
,
0
b011011
)
DEFINE_STRUCT_A64
(
TBZ_TBNZ
)
{
DEFINE_STRUCT_A64
(
TBZ_TBNZ
)
{
InstA64
rt
:
5
;
InstA64
rt
:
WideReg
;
InstA64
imm14
:
14
;
InstA64
imm14
:
14
;
InstA64
b40
:
5
;
InstA64
b40
:
5
;
InstA64
op
:
1
;
InstA64
op
:
1
;
...
@@ -149,7 +163,7 @@ DEFINE_STRUCT_A64(TBZ_TBNZ) {
...
@@ -149,7 +163,7 @@ DEFINE_STRUCT_A64(TBZ_TBNZ) {
DEFINE_OPCODE
(
LDR_LIT
,
0
b011000
)
DEFINE_OPCODE
(
LDR_LIT
,
0
b011000
)
DEFINE_STRUCT_A64
(
LDR_LIT
)
{
DEFINE_STRUCT_A64
(
LDR_LIT
)
{
InstA64
rt
:
5
;
InstA64
rt
:
WideReg
;
InstA64
imm19
:
19
;
InstA64
imm19
:
19
;
InstA64
opcode
:
6
;
InstA64
opcode
:
6
;
InstA64
op
:
2
;
InstA64
op
:
2
;
...
@@ -160,7 +174,7 @@ DEFINE_OPCODE(BR_BLR_RET_2, 0b11111000000)
...
@@ -160,7 +174,7 @@ DEFINE_OPCODE(BR_BLR_RET_2, 0b11111000000)
DEFINE_OPCODE
(
BR_BLR_RET_3
,
0
b00000
)
DEFINE_OPCODE
(
BR_BLR_RET_3
,
0
b00000
)
DEFINE_STRUCT_A64
(
BR_BLR_RET
)
{
DEFINE_STRUCT_A64
(
BR_BLR_RET
)
{
InstA64
opcode3
:
5
;
InstA64
opcode3
:
5
;
InstA64
rn
:
5
;
InstA64
rn
:
WideReg
;
InstA64
opcode2
:
11
;
InstA64
opcode2
:
11
;
InstA64
op
:
2
;
InstA64
op
:
2
;
InstA64
opcode1
:
9
;
InstA64
opcode1
:
9
;
...
@@ -169,8 +183,8 @@ DEFINE_STRUCT_A64(BR_BLR_RET) {
...
@@ -169,8 +183,8 @@ DEFINE_STRUCT_A64(BR_BLR_RET) {
DEFINE_OPCODE
(
STR_IMM
,
0
b111000000
)
DEFINE_OPCODE
(
STR_IMM
,
0
b111000000
)
DEFINE_STRUCT_A64
(
STR_IMM
)
{
DEFINE_STRUCT_A64
(
STR_IMM
)
{
InstA64
rt
:
5
;
InstA64
rt
:
WideReg
;
InstA64
rn
:
5
;
InstA64
rn
:
WideReg
;
InstA64
addrmode
:
2
;
InstA64
addrmode
:
2
;
InstA64
imm9
:
9
;
InstA64
imm9
:
9
;
InstA64
opcode
:
9
;
InstA64
opcode
:
9
;
...
@@ -179,8 +193,8 @@ DEFINE_STRUCT_A64(STR_IMM) {
...
@@ -179,8 +193,8 @@ DEFINE_STRUCT_A64(STR_IMM) {
DEFINE_OPCODE
(
STR_UIMM
,
0
b11100100
)
DEFINE_OPCODE
(
STR_UIMM
,
0
b11100100
)
DEFINE_STRUCT_A64
(
STR_UIMM
)
{
DEFINE_STRUCT_A64
(
STR_UIMM
)
{
InstA64
rt
:
5
;
InstA64
rt
:
WideReg
;
InstA64
rn
:
5
;
InstA64
rn
:
WideReg
;
InstA64
imm12
:
12
;
InstA64
imm12
:
12
;
InstA64
opcode
:
8
;
InstA64
opcode
:
8
;
InstA64
size
:
2
;
InstA64
size
:
2
;
...
...
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