Commit b41514d8 authored by swift_gan's avatar swift_gan Committed by swift_gan

[NativeHook]done t16 insts

parent da5a7aee
...@@ -10,11 +10,21 @@ enum InstCodeA32 { ...@@ -10,11 +10,21 @@ enum InstCodeA32 {
}; };
enum InstCodeT16 { enum InstCodeT16 {
BASE_SASMC,
DATA_PROC,
SPDIABE,
MISC,
B, B,
B_COND, B_COND,
BX_BLX, BX_BLX,
CBZ_CBNZ, CBZ_CBNZ,
LDR_LIT LDR_LIT,
//when rd = rn
ADD_IMM_RDN,
//rn = pc
ADR,
CMP_REG,
MOV_REG
}; };
enum InstCodeT32 { enum InstCodeT32 {
......
...@@ -29,6 +29,10 @@ DEFINE_OPCODE_T16(SPDIABE, 0b010001) ...@@ -29,6 +29,10 @@ DEFINE_OPCODE_T16(SPDIABE, 0b010001)
DEFINE_OPCODE_T16(MISC, 0b1011) DEFINE_OPCODE_T16(MISC, 0b1011)
#define DATA_PROC_FIELDS DEFINE_STRCUT_BASE_T16(6, 4)
#define T16_REG_WIDE 3
DEFINE_OPCODE_T16(B, 0b11100) DEFINE_OPCODE_T16(B, 0b11100)
DEFINE_STRUCT_T16(B) { DEFINE_STRUCT_T16(B) {
...@@ -57,7 +61,7 @@ DEFINE_OPCODE_T16(CBZ_CBNZ_1, 0b1011) ...@@ -57,7 +61,7 @@ DEFINE_OPCODE_T16(CBZ_CBNZ_1, 0b1011)
DEFINE_OPCODE_T16(CBZ_CBNZ_2, 0b0) DEFINE_OPCODE_T16(CBZ_CBNZ_2, 0b0)
DEFINE_OPCODE_T16(CBZ_CBNZ_3, 0b1) DEFINE_OPCODE_T16(CBZ_CBNZ_3, 0b1)
DEFINE_STRUCT_T16(CBZ_CBNZ) { DEFINE_STRUCT_T16(CBZ_CBNZ) {
InstT16 rn:3; InstT16 rn:T16_REG_WIDE;
InstT16 imm5:5; InstT16 imm5:5;
InstT16 opcode3:1; InstT16 opcode3:1;
InstT16 i:1; InstT16 i:1;
...@@ -69,10 +73,40 @@ DEFINE_STRUCT_T16(CBZ_CBNZ) { ...@@ -69,10 +73,40 @@ DEFINE_STRUCT_T16(CBZ_CBNZ) {
DEFINE_OPCODE_T16(LDR_LIT, 0b01001) DEFINE_OPCODE_T16(LDR_LIT, 0b01001)
DEFINE_STRUCT_T16(LDR_LIT) { DEFINE_STRUCT_T16(LDR_LIT) {
InstT16 imm8:8; InstT16 imm8:8;
InstT16 rt:3; InstT16 rt:T16_REG_WIDE;
InstT16 opcode:5;
};
DEFINE_OPCODE_T16(ADD_IMM_RDN, 0b00110)
DEFINE_STRUCT_T16(ADD_IMM_RDN) {
InstT16 imm8:8;
InstT16 rdn:T16_REG_WIDE;
InstT16 opcode:5;
};
DEFINE_OPCODE_T16(ADR, 0b10100)
DEFINE_STRUCT_T16(ADR) {
InstT16 imm8:8;
InstT16 rd:T16_REG_WIDE;
InstT16 opcode:5; InstT16 opcode:5;
}; };
DEFINE_OPCODE_T16(CMP_REG, 0b1010)
DEFINE_STRUCT_T16(CMP_REG) {
InstT16 rn:T16_REG_WIDE;
InstT16 rm:T16_REG_WIDE;
DATA_PROC_FIELDS
};
DEFINE_OPCODE_T16(MOV_REG, 0b10)
DEFINE_STRUCT_T16(MOV_REG) {
InstT16 rd:3;
InstT16 rm:4;
InstT16 D:1;
DEFINE_STRCUT_BASE_T16(6, 2)
};
......
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
#include "inst_t16.h" #include "inst_t16.h"
#include "arm32_base.h" #include "arm32_base.h"
#include "register_list_a32.h"
#define SET_BASE_OPCODE(X) get()->opcode_base = OPCODE_T16(X) #define SET_BASE_OPCODE(X) get()->opcode_base = OPCODE_T16(X)
...@@ -11,7 +12,7 @@ ...@@ -11,7 +12,7 @@
#define SET_OPCODE_MULTI(X, INDEX) get()->opcode##INDEX = OPCODE_T16(X##_##INDEX) #define SET_OPCODE_MULTI(X, INDEX) get()->opcode##INDEX = OPCODE_T16(X##_##INDEX)
using namespace SandHook::AsmA32; using namespace SandHook::AsmA32;
using namespace SandHook::RegistersA32;
//B //B
...@@ -153,7 +154,7 @@ T16_LDR_LIT::T16_LDR_LIT(Off offset, RegisterA32 &rt) : offset(offset), rt(&rt) ...@@ -153,7 +154,7 @@ T16_LDR_LIT::T16_LDR_LIT(Off offset, RegisterA32 &rt) : offset(offset), rt(&rt)
} }
Off T16_LDR_LIT::getImmPCOffset() { Off T16_LDR_LIT::getImmPCOffset() {
return DECODE_OFFSET(8, 2); return get()->imm8 >> 2;
} }
Addr T16_LDR_LIT::getImmPCOffsetTarget() { Addr T16_LDR_LIT::getImmPCOffsetTarget() {
...@@ -173,4 +174,111 @@ void T16_LDR_LIT::decode(T16_STRUCT_LDR_LIT *inst) { ...@@ -173,4 +174,111 @@ void T16_LDR_LIT::decode(T16_STRUCT_LDR_LIT *inst) {
void T16_LDR_LIT::assembler() { void T16_LDR_LIT::assembler() {
SET_OPCODE(LDR_LIT); SET_OPCODE(LDR_LIT);
ENCODE_RT; ENCODE_RT;
ENCODE_OFFSET(8, 2);
}
//ADD IMM RD = RN
T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(T16_STRUCT_ADD_IMM_RDN *inst) : InstructionT16(inst) {
decode(inst);
}
T16_ADD_IMM_RDN::T16_ADD_IMM_RDN(RegisterA32 *rdn, S32 imm32) : rdn(rdn), imm32(imm32) {}
void T16_ADD_IMM_RDN::decode(T16_STRUCT_ADD_IMM_RDN *inst) {
imm32 = inst->imm8;
}
void T16_ADD_IMM_RDN::assembler() {
SET_OPCODE(ADD_IMM_RDN);
get()->imm8 = imm32;
}
//ADR
T16_ADR::T16_ADR(T16_STRUCT_ADR *inst) : T16_INST_PC_REL(inst) {
decode(inst);
}
T16_ADR::T16_ADR(RegisterA32 *rd, Off offset) : rd(rd), offset(offset) {}
T16_ADR::T16_ADR(RegisterA32 *rd, Label &label) : rd(rd) {
bindLabel(label);
}
Off T16_ADR::getImmPCOffset() {
return COMBINE(get()->imm8, 0 ,2);
}
Addr T16_ADR::getImmPCOffsetTarget() {
return RoundDown((Addr) getPC() + offset, 4);
}
void T16_ADR::decode(T16_STRUCT_ADR *inst) {
offset = getImmPCOffset();
DECODE_RD(Reg);
}
void T16_ADR::assembler() {
SET_OPCODE(ADR);
ENCODE_RD;
get()->imm8 = (U32)offset >> 2;
}
T16_CMP_REG::T16_CMP_REG() {}
T16_CMP_REG::T16_CMP_REG(T16_STRUCT_CMP_REG *inst) : InstructionT16(inst) {
decode(inst);
}
T16_CMP_REG::T16_CMP_REG(RegisterA32 &rm, RegisterA32 &rn) : rm(&rm), rn(&rn) {}
void T16_CMP_REG::decode(T16_STRUCT_CMP_REG *inst) {
DECODE_RM(Reg);
DECODE_RN(Reg);
}
void T16_CMP_REG::assembler() {
SET_BASE_OPCODE(DATA_PROC);
SET_OPCODE(CMP_REG);
ENCODE_RM;
ENCODE_RN;
}
bool T16_CMP_REG::pcRelate() {
return rn == &PC || rm == &PC;
} }
//MOV REG
T16_MOV_REG::T16_MOV_REG(T16_STRUCT_MOV_REG *inst) : InstructionT16(inst) {
decode(inst);
}
T16_MOV_REG::T16_MOV_REG(RegisterA32 &rd, RegisterA32 &rm) : rm(&rm), rd(&rd) {
}
void T16_MOV_REG::decode(T16_STRUCT_MOV_REG *inst) {
DECODE_RM(Reg);
rd = Reg(static_cast<U8>(COMBINE(inst->D, inst->rd, 3)));
}
void T16_MOV_REG::assembler() {
SET_BASE_OPCODE(DATA_PROC);
SET_OPCODE(MOV_REG);
ENCODE_RM;
}
bool T16_MOV_REG::pcRelate() {
return rd == &PC || rm == &PC;
}
...@@ -155,7 +155,7 @@ namespace SandHook { ...@@ -155,7 +155,7 @@ namespace SandHook {
}; };
class INST_T16(BX_BLX) : T16_INST_PC_REL<STRUCT_T16(BX_BLX)> { class INST_T16(BX_BLX) : public T16_INST_PC_REL<STRUCT_T16(BX_BLX)> {
public: public:
enum OP { enum OP {
...@@ -213,7 +213,7 @@ namespace SandHook { ...@@ -213,7 +213,7 @@ namespace SandHook {
}; };
class INST_T16(LDR_LIT) : T16_INST_PC_REL<STRUCT_T16(LDR_LIT)> { class INST_T16(LDR_LIT) : public T16_INST_PC_REL<STRUCT_T16(LDR_LIT)> {
public: public:
T16_LDR_LIT(T16_STRUCT_LDR_LIT *inst); T16_LDR_LIT(T16_STRUCT_LDR_LIT *inst);
...@@ -241,6 +241,95 @@ namespace SandHook { ...@@ -241,6 +241,95 @@ namespace SandHook {
RegisterA32* rt; RegisterA32* rt;
}; };
class INST_T16(ADD_IMM_RDN) : public InstructionT16<STRUCT_T16(ADD_IMM_RDN)> {
public:
T16_ADD_IMM_RDN(T16_STRUCT_ADD_IMM_RDN *inst);
T16_ADD_IMM_RDN(RegisterA32 *rdn, S32 imm32);
void decode(T16_STRUCT_ADD_IMM_RDN *inst) override;
void assembler() override;
public:
RegisterA32* rdn;
S32 imm32;
};
class INST_T16(ADR) : public T16_INST_PC_REL<STRUCT_T16(ADR)> {
public:
T16_ADR(T16_STRUCT_ADR *inst);
T16_ADR(RegisterA32 *rd, Off offset);
T16_ADR(RegisterA32 *rd, Label& label);
DEFINE_IS(ADR)
DEFINE_INST_CODE(ADR)
Off getImmPCOffset() override;
Addr getImmPCOffsetTarget() override;
void decode(T16_STRUCT_ADR *inst) override;
void assembler() override;
public:
RegisterA32* rd;
Off offset;
};
class INST_T16(CMP_REG) : public InstructionT16<STRUCT_T16(CMP_REG)> {
public:
T16_CMP_REG();
T16_CMP_REG(T16_STRUCT_CMP_REG *inst);
T16_CMP_REG(RegisterA32 &rm, RegisterA32 &rn);
DEFINE_INST_CODE(CMP_REG)
DEFINE_IS_EXT(CMP_REG, TEST_INST_FIELD(opcode_base, OPCODE_T16(DATA_PROC)) && TEST_INST_FIELD(opcode, OPCODE_T16(CMP_REG)))
void decode(T16_STRUCT_CMP_REG *inst) override;
void assembler() override;
bool pcRelate() override;
public:
RegisterA32* rm;
RegisterA32* rn;
};
class INST_T16(MOV_REG) : public InstructionT16<STRUCT_T16(MOV_REG)> {
public:
T16_MOV_REG(T16_STRUCT_MOV_REG *inst);
T16_MOV_REG(RegisterA32 &rd, RegisterA32 &rm);
DEFINE_INST_CODE(MOV_REG)
DEFINE_IS_EXT(MOV_REG, TEST_INST_FIELD(opcode_base, OPCODE_T16(DATA_PROC)) && TEST_INST_FIELD(opcode, OPCODE_T16(MOV_REG)))
void decode(T16_STRUCT_MOV_REG *inst) override;
void assembler() override;
bool pcRelate() override;
public:
RegisterA32* rd;
RegisterA32* rm;
};
} }
} }
......
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