Commit b9946009 authored by swift_gan's avatar swift_gan Committed by swift_gan

add inst SUBS Reg

parent e8b846a7
......@@ -459,3 +459,38 @@ void A64_MOV_REG::assembler() {
get()->rd = rd->getCode();
get()->rm = rm->getCode();
}
A64_SUBS_EXT_REG::A64_SUBS_EXT_REG() {}
A64_SUBS_EXT_REG::A64_SUBS_EXT_REG(STRUCT_A64(SUBS_EXT_REG) &inst) : InstructionA64(&inst) {}
A64_SUBS_EXT_REG::A64_SUBS_EXT_REG(RegisterA64 &rd, RegisterA64 &rn, const Operand &operand,
FlagsUpdate flagsUpdate) : rd(&rd), rn(&rn), operand(operand),
flagsUpdate(flagsUpdate) {}
void A64_SUBS_EXT_REG::decode(STRUCT_A64(SUBS_EXT_REG) *inst) {
if (inst->sf == 1) {
rd = XReg(static_cast<U8>(inst->rd));
rn = XReg(static_cast<U8>(inst->rn));
operand.reg = XReg(static_cast<U8>(inst->rm));
} else {
rd = WReg(static_cast<U8>(inst->rd));
rn = WReg(static_cast<U8>(inst->rn));
operand.reg = XReg(static_cast<U8>(inst->rm));
}
operand.extend = Extend(inst->option);
INST_ASSERT(inst->imm3 > 4);
operand.shift = Shift(inst->imm3);
}
void A64_SUBS_EXT_REG::assembler() {
SET_OPCODE(SUBS_EXT_REG);
get()->sf = rd->isX() ? 1 : 0;
get()->option = operand.extend;
get()->imm3 = operand.shift;
get()->rm = operand.reg->getCode();
get()->rn = rn->getCode();
get()->rd = rd->getCode();
}
......@@ -84,8 +84,19 @@ namespace SandHook {
enum MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH};
enum FPTrapFlags {
EnableTrap = 1,
DisableTrap = 0
};
enum FlagsUpdate {
SetFlags = 1,
LeaveFlags = 0
};
class Operand {
public:
inline explicit Operand(){};
inline explicit Operand(S64 imm)
: immediate(imm), reg(&UnknowRegiser), shift(NO_SHIFT), extend(NO_EXTEND), shift_extend_imm(0) {}
inline Operand(RegisterA64* reg, Shift shift = LSL, int32_t imm = 0)
......@@ -581,6 +592,32 @@ namespace SandHook {
RegisterA64* rm;
};
class INST_A64(SUBS_EXT_REG) : InstructionA64<STRUCT_A64(SUBS_EXT_REG)> {
public:
A64_SUBS_EXT_REG();
A64_SUBS_EXT_REG(STRUCT_A64(SUBS_EXT_REG) &inst);
A64_SUBS_EXT_REG(RegisterA64 &rd, RegisterA64 &rn, const Operand &operand,
FlagsUpdate flagsUpdate);
DEFINE_IS(SUBS_EXT_REG)
DEFINE_INST_CODE(SUBS_EXT_REG)
void decode(A64_STRUCT_SUBS_EXT_REG *inst) override;
void assembler() override;
public:
RegisterA64* rd;
RegisterA64* rn;
Operand operand = Operand();
FlagsUpdate flagsUpdate;
};
}
}
......
......@@ -20,6 +20,7 @@ enum InstCodeA64 {
BR_BLR_RET,
CBZ_CBNZ,
TBZ_TBNZ,
SUBS_EXT_REG
};
// Generic fields.
......
......@@ -200,5 +200,16 @@ DEFINE_STRUCT_A64(STR_UIMM) {
InstA64 size:2;
};
DEFINE_OPCODE(SUBS_EXT_REG, 0b1101011001)
DEFINE_STRUCT_A64(SUBS_EXT_REG) {
InstA64 rd:WideReg;
InstA64 rn:WideReg;
InstA64 imm3:3;
InstA64 option:3;
InstA64 rm:WideReg;
InstA64 opcode:10;
InstA64 sf:1;
};
#endif //SANDHOOK_NH_INST_AARCH64_H
......@@ -18,4 +18,7 @@ XRegister LR = X30;
//zero reg
XRegister XZR = X31;
WRegister WZR = W31;
RegisterA64 UnknowRegiser = RegisterA64(38);
\ No newline at end of file
RegisterA64 UnknowRegiser = RegisterA64(38);
//cmp....
#define ZeroRegFor(X) X.isX() ? XZR : WZR
\ No newline at end of file
......@@ -31,6 +31,7 @@ DCHECK(X,V, valid = false;)
#define INST_ASSERT(COND) \
if (COND) { \
valid = false; \
return; \
}
namespace SandHook {
......
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