Commit c98a07b9 authored by swift_gan's avatar swift_gan Committed by swift_gan

[NativeHook]add fix inst add reg rdn

parent 29adbb4f
......@@ -52,6 +52,7 @@ void Arm32Decoder::decode(void *codeStart, Addr codeLen, InstVisitor &visitor, b
CASE_T16(LDR_LIT)
CASE_T16(ADD_IMM_RDN)
CASE_T16(ADR)
CASE_T16(ADD_REG_RDN)
if (!onlyPcRelInst) {
CASE_T16(ADD_REG)
CASE_T16(CMP_REG)
......
......@@ -29,7 +29,8 @@ enum class InstCodeT16 {
MOV_IMM,
MOV_REG,
POP,
PUSH
PUSH,
ADD_REG_RDN
};
enum class InstCodeT32 {
......
......@@ -136,6 +136,14 @@ DEFINE_STRUCT_T16(ADD_REG) {
InstT16 opcode:7;
};
DEFINE_OPCODE_T16(ADD_REG_RDN, 0b01000100)
DEFINE_STRUCT_T16(ADD_REG_RDN) {
InstT16 rdn:T16_REG_WIDE;
InstT16 rm:4;
InstT16 unknow:1;
InstT16 opcode:8;
};
DEFINE_OPCODE_T16(POP, 0b1011110)
DEFINE_STRUCT_T16(POP) {
InstT16 regs:8;
......
......@@ -384,4 +384,27 @@ void T16_PUSH::assembler() {
U16 regs = registerList.GetList();
get()->regs = BITS(regs, 0, 7);
get()->M = BIT(regs, 14);
}
\ No newline at end of file
}
// Add reg rdn T2
T16_ADD_REG_RDN::T16_ADD_REG_RDN(T16_STRUCT_ADD_REG_RDN *inst) : InstructionT16(inst) {
decode(inst);
}
T16_ADD_REG_RDN::T16_ADD_REG_RDN(RegisterA32 &rdn, RegisterA32 &rm) : rdn(&rdn), rm(&rm) {}
bool T16_ADD_REG_RDN::pcRelate() {
return *rm == PC;
}
void T16_ADD_REG_RDN::decode(T16_STRUCT_ADD_REG_RDN *inst) {
DECODE_RM(Reg);
rdn = Reg(inst->rdn);
}
void T16_ADD_REG_RDN::assembler() {
SET_OPCODE(ADD_REG_RDN);
ENCODE_RM;
get()->rdn = rdn->getCode();
}
......@@ -444,6 +444,30 @@ namespace SandHook {
RegisterList registerList;
};
class INST_T16(ADD_REG_RDN) : public InstructionT16<STRUCT_T16(ADD_REG_RDN)> {
public:
T16_ADD_REG_RDN(T16_STRUCT_ADD_REG_RDN *inst);
T16_ADD_REG_RDN(RegisterA32 &rdn, RegisterA32 &rm);
DEFINE_IS(ADD_REG_RDN)
DEFINE_INST_CODE(ADD_REG_RDN)
bool pcRelate() override;
void decode(T16_STRUCT_ADD_REG_RDN *inst) override;
void assembler() override;
public:
RegisterA32* rdn;
RegisterA32* rm;
};
}
}
......
......@@ -79,6 +79,7 @@ void* CodeRelocateA32::relocate(Instruction<Base> *instruction, void *toPc) thro
CASE(T16, CBZ_CBNZ)
CASE(T16, ADR)
CASE(T16, LDR_LIT)
CASE(T16, ADD_REG_RDN)
default:
__ Emit(instruction);
instruction->ref();
......@@ -198,6 +199,23 @@ IMPL_RELOCATE(T16, ADR) {
}
IMPL_RELOCATE(T16, ADD_REG_RDN) {
if (*inst->rm != PC) {
inst->ref();
__ Emit(reinterpret_cast<Instruction<Base>*>(inst));
return;
}
RegisterA32& tmpReg = *inst->rdn != R0 ? R0 : R1;
__ Push(tmpReg);
__ Mov(tmpReg,(Addr)inst->getPC());
__ Add(*inst->rdn, *inst->rdn, tmpReg);
__ Pop(tmpReg);
}
IMPL_RELOCATE(T32, B32) {
if (inRelocateRange(CODE_OFFSET(inst), sizeof(InstT16))) {
......@@ -239,7 +257,7 @@ IMPL_RELOCATE(T32, B32) {
IMPL_RELOCATE(T32, LDR_LIT) {
if (inRelocateRange(CODE_OFFSET(inst), sizeof(InstT16))) {
if (inRelocateRange(CODE_OFFSET(inst), sizeof(Addr))) {
inst->ref();
inst->bindLabel(*getLaterBindLabel(CODE_OFFSET(inst) + curOffset));
__ Emit(reinterpret_cast<Instruction<Base>*>(inst));
......
......@@ -41,6 +41,8 @@ namespace SandHook {
DEFINE_RELOCATE(T16, ADR)
DEFINE_RELOCATE(T16, ADD_REG_RDN)
DEFINE_RELOCATE(T32, B32)
DEFINE_RELOCATE(T32, LDR_LIT)
......
......@@ -62,7 +62,7 @@ namespace SandHook {
}
bool operator!=(const Register &rhs) const {
return !(rhs == *this);
return code != rhs.code;
}
virtual void setData(Data data) {
......
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