Commit ebafba80 authored by swift_gan's avatar swift_gan Committed by swift_gan

[NativeHook]add inst add adds sub subs

parent f1ff5627
......@@ -207,14 +207,30 @@ void AssemblerA64::Subs(RegisterA64 &rd, RegisterA64 &rn, const Operand &operand
Emit(reinterpret_cast<Unit<Base> *>(new INST_A64(SUB_EXT_REG)(rd, rn, operand, SetFlags)));
}
void AssemblerA64::stp(RegisterA64 &rt1, RegisterA64 &rt2, const MemOperand operand) {
void AssemblerA64::Stp(RegisterA64 &rt1, RegisterA64 &rt2, const MemOperand operand) {
Emit(reinterpret_cast<Unit<Base> *>(new INST_A64(STP_LDP)(INST_A64(STP_LDP)::STP, rt1, rt2, operand)));
}
void AssemblerA64::ldp(RegisterA64 &rt1, RegisterA64 &rt2, const MemOperand operand) {
void AssemblerA64::Ldp(RegisterA64 &rt1, RegisterA64 &rt2, const MemOperand operand) {
Emit(reinterpret_cast<Unit<Base> *>(new INST_A64(STP_LDP)(INST_A64(STP_LDP)::LDP, rt1, rt2, operand)));
}
void AssemblerA64::Add(RegisterA64 &rd, const Operand &operand) {
Emit(reinterpret_cast<Unit<Base> *>(new INST_A64(ADD_SUB_IMM)(INST_A64(ADD_SUB_IMM)::ADD, INST_A64(ADD_SUB_IMM)::UnSign, rd, operand)));
}
void AssemblerA64::Adds(RegisterA64 &rd, const Operand &operand) {
Emit(reinterpret_cast<Unit<Base> *>(new INST_A64(ADD_SUB_IMM)(INST_A64(ADD_SUB_IMM)::ADD, INST_A64(ADD_SUB_IMM)::Sign, rd, operand)));
}
void AssemblerA64::Sub(RegisterA64 &rd, const Operand &operand) {
Emit(reinterpret_cast<Unit<Base> *>(new INST_A64(ADD_SUB_IMM)(INST_A64(ADD_SUB_IMM)::SUB, INST_A64(ADD_SUB_IMM)::UnSign, rd, operand)));
}
void AssemblerA64::Subs(RegisterA64 &rd, const Operand &operand) {
Emit(reinterpret_cast<Unit<Base> *>(new INST_A64(ADD_SUB_IMM)(INST_A64(ADD_SUB_IMM)::SUB, INST_A64(ADD_SUB_IMM)::Sign, rd, operand)));
}
......@@ -74,8 +74,14 @@ namespace SandHook {
void Subs(RegisterA64& rd, RegisterA64& rn, const Operand& operand);
void Cmp(RegisterA64& rn, const Operand& operand);
void stp(RegisterA64& rt1, RegisterA64& rt2, const MemOperand operand);
void ldp(RegisterA64& rt1, RegisterA64& rt2, const MemOperand operand);
void Stp(RegisterA64& rt1, RegisterA64& rt2, const MemOperand operand);
void Ldp(RegisterA64& rt1, RegisterA64& rt2, const MemOperand operand);
void Add(RegisterA64& rd, const Operand& operand);
void Adds(RegisterA64& rd, const Operand& operand);
void Sub(RegisterA64& rd, const Operand& operand);
void Subs(RegisterA64& rd, const Operand& operand);
public:
......
......@@ -44,6 +44,8 @@ void Arm64Decoder::decode(void *codeStart, Addr codeLen, InstVisitor &visitor, b
CASE(SVC)
CASE(EXCEPTION_GEN)
CASE(STP_LDP)
CASE(ADD_SUB_IMM)
label_matched:
if (unit == nullptr) {
unit = reinterpret_cast<Unit<Base> *>(new INST_A64(UNKNOW)(*reinterpret_cast<STRUCT_A64(UNKNOW) *>(pc)));
......
......@@ -847,3 +847,51 @@ void A64_STP_LDP::assembler() {
}
get()->imm7 = TruncateToUint7(operand.offset >> (rt1->isX() ? 3 : 2));
}
A64_ADD_SUB_IMM::A64_ADD_SUB_IMM() {}
A64_ADD_SUB_IMM::A64_ADD_SUB_IMM(A64_STRUCT_ADD_SUB_IMM &inst) : InstructionA64(&inst) {
decode(&inst);
}
A64_ADD_SUB_IMM::A64_ADD_SUB_IMM(A64_ADD_SUB_IMM::OP op, A64_ADD_SUB_IMM::S sign, RegisterA64 &rd,
const Operand &operand) : op(op), sign(sign), rd(&rd), operand(operand) {}
void A64_ADD_SUB_IMM::decode(A64_STRUCT_ADD_SUB_IMM *inst) {
DECODE_OP;
if (inst->sf == Size64) {
DECODE_RD(XReg);
operand.reg = XReg(inst->rn);
} else {
DECODE_RD(XReg);
operand.reg = WReg(inst->rn);
}
sign = S(inst->S);
DECODE_SHIFT;
if (operand.shift == LSL) {
operand.immediate = get()->imm12;
} else if (operand.shift == LSR) {
operand.immediate = get()->imm12 << 12;
} else {
valid = false;
}
}
void A64_ADD_SUB_IMM::assembler() {
SET_OPCODE(ADD_SUB_IMM);
ENCODE_OP;
ENCODE_RD;
get()->rn = operand.reg->getCode();
get()->sf = rd->isX() ? Size64 : Size32;
get()->S = sign;
ENCODE_SHIFT;
if (operand.shift == LSL) {
get()->imm12 = static_cast<InstA64>(operand.immediate);
} else if (operand.shift == LSR) {
get()->imm12 = static_cast<InstA64>(operand.immediate) >> 12;
} else {
valid = false;
}
}
......@@ -777,6 +777,46 @@ namespace SandHook {
MemOperand operand;
};
class INST_A64(ADD_SUB_IMM) : public InstructionA64<STRUCT_A64(ADD_SUB_IMM)> {
public:
enum OP {
ADD = 0b0,
SUB = 0b1
};
enum S {
Sign = 0b0,
UnSign = 0b1
};
enum Size {
Size32 = 0b0,
Size64 = 0b1
};
A64_ADD_SUB_IMM();
A64_ADD_SUB_IMM(A64_STRUCT_ADD_SUB_IMM &inst);
A64_ADD_SUB_IMM(OP op, S sign, RegisterA64 &rd, const Operand &operand);
DEFINE_IS(ADD_SUB_IMM)
DEFINE_INST_CODE(ADD_SUB_IMM)
void decode(A64_STRUCT_ADD_SUB_IMM *inst) override;
void assembler() override;
public:
OP op;
S sign;
RegisterA64* rd;
Operand operand;
};
}
}
......
......@@ -28,6 +28,7 @@ enum class InstCodeA64 {
EXCEPTION_GEN,
SVC,
STP_LDP,
ADD_SUB_IMM
};
#endif //SANDHOOK_NH_INST_CODE_ARM64_H
......@@ -215,6 +215,18 @@ DEFINE_STRUCT_A64(STP_LDP) {
InstA64 size:2;
};
DEFINE_OPCODE_A64(ADD_SUB_IMM, 0b10001)
DEFINE_STRUCT_A64(ADD_SUB_IMM) {
InstA64 rd:WideReg;
InstA64 rn:WideReg;
InstA64 imm12:12;
InstA64 shift:2;
InstA64 opcode:5;
InstA64 S:2;
InstA64 op:1;
InstA64 sf:1;
};
#endif //SANDHOOK_NH_INST_AARCH64_H
......@@ -66,5 +66,8 @@ enum AddrMode { Offset, PreIndex, PostIndex, NonAddrMode};
#define DECODE_OP op = OP(inst->op)
#define ENCODE_OP get()->op = op
#define DECODE_SHIFT operand.shift = Shift(inst->shift)
#define ENCODE_SHIFT get()->shift = operand.shift
#endif //SANDHOOK_ARM_BASE_H
include ':app', ':hooklib', ':hookers', ':annotation', ':xposedcompat', ':nativehook'
include ':app', ':hooklib', ':hookers', ':annotation', ':xposedcompat', ':nativehook', ':xposedcompat_new'
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