Commit 6b0d6bbf authored by swift_gan's avatar swift_gan Committed by swift_gan

tweak code

parent a495dc5c
......@@ -21,6 +21,7 @@ add_library( # Sets the name of the library.
src/main/cpp/decoder/decoder.cpp
src/main/cpp/archs/arm64/inst/inst_arm64.cpp
src/main/cpp/archs/arm64/register/register_a64.cpp
src/main/cpp/archs/arm64/register/register_list_a64.cpp
src/main/cpp/archs/arm64/decoder/decoder_arm64.cpp
)
......
......@@ -3,7 +3,6 @@
//
#include "inst_arm64.h"
#include "../register/register_a64.h"
#define SET_OPCODE(X) get()->opcode = OPCODE_A64(X)
......@@ -273,3 +272,16 @@ void A64_LDR_LIT::assembler() {
get()->op = op;
get()->imm19 = TruncateToUint19(offset);
}
// STR IMM
A64_STR_IMM::A64_STR_IMM() {}
A64_STR_IMM::A64_STR_IMM(A64_STRUCT_STR_IMM *inst) : InstructionA64(inst) {
decode(inst);
}
A64_STR_IMM::A64_STR_IMM(RegisterA64 *rt, const MemOperand &oprand) : rt(rt), oprand(oprand) {
assembler();
}
......@@ -5,12 +5,10 @@
#ifndef SANDHOOK_NH_INST_ARM64_H
#define SANDHOOK_NH_INST_ARM64_H
#include <register.h>
#include "inst_struct_aarch64.h"
#include "../../../asm/instruction.h"
#include "../../../includes/base.h"
#include "../register/register_a64.h"
#include "../../../../../../../hooklib/src/main/cpp/includes/inst.h"
#include "../register/register_list_a64.h"
#define INST_A64(X) A64_##X
......@@ -71,6 +69,102 @@ namespace SandHook {
enum AddrMode { Offset, PreIndex, PostIndex };
class Operand {
public:
inline explicit Operand(S64 imm)
: immediate_(imm), reg_(&UnknowRegiser), shift_(NO_SHIFT), extend_(NO_EXTEND), shift_extent_imm_(0) {}
inline Operand(RegisterA64* reg, Shift shift = LSL, int32_t imm = 0)
: immediate_(0), reg_(reg), shift_(shift), extend_(NO_EXTEND), shift_extent_imm_(imm) {}
inline Operand(RegisterA64* reg, Extend extend, int32_t imm = 0)
: immediate_(0), reg_(reg), shift_(NO_SHIFT), extend_(extend), shift_extent_imm_(imm) {}
// =====
bool IsImmediate() const { return reg_->is(UnknowRegiser); }
bool IsShiftedRegister() const { return /* reg_.IsValid() && */ (shift_ != NO_SHIFT); }
bool IsExtendedRegister() const { return /* reg_.IsValid() && */ (extend_ != NO_EXTEND); }
// =====
RegisterA64* reg() const {
return reg_;
}
S64 Immediate() const { return immediate_; }
Shift shift() const {
return shift_;
}
Extend extend() const {
return extend_;
}
int32_t shift_extend_imm() const { return shift_extent_imm_; }
private:
S64 immediate_;
RegisterA64* reg_;
Shift shift_;
Extend extend_;
int32_t shift_extent_imm_;
};
class MemOperand {
public:
inline explicit MemOperand(RegisterA64* base, int64_t offset = 0, AddrMode addrmode = Offset)
: base_(base), regoffset_(&UnknowRegiser), offset_(offset), addrmode_(addrmode), shift_(NO_SHIFT),
extend_(NO_EXTEND), shift_extend_imm_(0) {}
inline explicit MemOperand(RegisterA64* base, RegisterA64* regoffset, Extend extend, unsigned extend_imm)
: base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset), shift_(NO_SHIFT), extend_(extend),
shift_extend_imm_(extend_imm) {}
inline explicit MemOperand(RegisterA64* base, RegisterA64* regoffset, Shift shift = LSL, unsigned shift_imm = 0)
: base_(base), regoffset_(regoffset), offset_(0), addrmode_(Offset), shift_(shift), extend_(NO_EXTEND),
shift_extend_imm_(shift_imm) {}
inline explicit MemOperand(RegisterA64* base, const Operand &offset, AddrMode addrmode = Offset)
: base_(base), regoffset_(&UnknowRegiser), addrmode_(addrmode) {
if (offset.IsShiftedRegister()) {
regoffset_ = offset.reg();
shift_ = offset.shift();
shift_extend_imm_ = offset.shift_extend_imm();
extend_ = NO_EXTEND;
offset_ = 0;
} else if (offset.IsExtendedRegister()) {
regoffset_ = offset.reg();
extend_ = offset.extend();
shift_extend_imm_ = offset.shift_extend_imm();
shift_ = NO_SHIFT;
offset_ = 0;
}
}
const RegisterA64* base() const { return base_; }
const RegisterA64* regoffset() const { return regoffset_; }
int64_t offset() const { return offset_; }
AddrMode addrmode() const { return addrmode_; }
Shift shift() const { return shift_; }
Extend extend() const { return extend_; }
unsigned shift_extend_imm() const { return shift_extend_imm_; }
// =====
bool IsImmediateOffset() const { return (addrmode_ == Offset); }
bool IsRegisterOffset() const { return (addrmode_ == Offset); }
bool IsPreIndex() const { return addrmode_ == PreIndex; }
bool IsPostIndex() const { return addrmode_ == PostIndex; }
private:
RegisterA64* base_;
RegisterA64* regoffset_;
int64_t offset_;
AddrMode addrmode_;
Shift shift_;
Extend extend_;
int32_t shift_extend_imm_;
};
template <typename Inst>
class A64_INST_PC_REL : public InstructionA64<Inst> {
......@@ -122,7 +216,7 @@ namespace SandHook {
void assembler() override;
private:
public:
OP op;
RegisterA64* rd;
int imme;
......@@ -184,7 +278,7 @@ namespace SandHook {
return rd;
}
private:
public:
//can be 16/32/64/128
//hw = shift / 16
U8 shift;
......@@ -230,7 +324,7 @@ namespace SandHook {
void assembler() override;
private:
public:
OP op;
ADDR offset;
};
......@@ -262,7 +356,7 @@ namespace SandHook {
void assembler() override;
private:
public:
OP op;
ADDR offset;
RegisterA64* rt;
......@@ -289,7 +383,7 @@ namespace SandHook {
void assembler() override;
private:
public:
Condition condition;
ADDR offset;
};
......@@ -321,7 +415,7 @@ namespace SandHook {
void assembler() override;
private:
public:
OP op;
RegisterA64* rt;
U32 bit;
......@@ -366,12 +460,27 @@ namespace SandHook {
void assembler() override;
private:
public:
OP op;
RegisterA64* rt;
ADDR offset;
};
class INST_A64(STR_IMM) : public InstructionA64<STRUCT_A64(STR_IMM)> {
public:
A64_STR_IMM();
A64_STR_IMM(A64_STRUCT_STR_IMM *inst);
A64_STR_IMM(RegisterA64 *rt, const MemOperand &oprand);
public:
RegisterA64* rt;
MemOperand oprand = MemOperand(nullptr);
};
}
}
......
......@@ -14,10 +14,10 @@ RegisterA64::RegisterA64(U8 code) : Register(code) {}
XRegister* XRegister::registers[AARCH64_REGISTER_COUNT] = {
#define DEFINE_REGISTERS(N) \
#define DEFINE_REGISTERS_X(N) \
&X##N,
AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS)
#undef DEFINE_REGISTERS
AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS_X)
#undef DEFINE_REGISTERS_X
};
XRegister::XRegister(U8 code) : RegisterA64(code) {}
......@@ -31,10 +31,10 @@ U8 XRegister::getWide() {
WRegister* WRegister::registers[AARCH64_REGISTER_COUNT] = {
#define DEFINE_REGISTERS(N) \
#define DEFINE_REGISTERS_W(N) \
&W##N,
AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS)
#undef DEFINE_REGISTERS
AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS_W)
#undef DEFINE_REGISTERS_W
};
WRegister::WRegister(U8 code) : RegisterA64(code) {}
......
......@@ -7,17 +7,6 @@
#include "register.h"
// clang-format off
#define AARCH64_REGISTER_COUNT 32
#define AARCH64_REGISTER_CODE_LIST(R) \
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
namespace SandHook {
namespace Asm {
......
//
// Created by swift on 2019/5/9.
//
#include "register_list_a64.h"
#define INIT_REGISTERS(N) \
WRegister W##N = WRegister(N); \
XRegister X##N = XRegister(N);
AARCH64_REGISTER_CODE_LIST(INIT_REGISTERS)
#undef INIT_REGISTERS
WRegister WSP = WRegister(RegisterA64::kSPRegInternalCode);
XRegister SP = XRegister(RegisterA64::kSPRegInternalCode);
XRegister IP0 = X16;
XRegister IP1 = X17;
XRegister LR = X30;
//zero reg
XRegister XZR = X31;
WRegister WZR = W31;
RegisterA64 UnknowRegiser = RegisterA64(250);
\ No newline at end of file
......@@ -10,19 +10,32 @@
using namespace SandHook::Asm;
// clang-format off
#define AARCH64_REGISTER_COUNT 32
#define AARCH64_REGISTER_CODE_LIST(R) \
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
#define DEFINE_REGISTERS(N) \
WRegister W##N(N); \
XRegister X##N(N);
AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS)
extern WRegister W##N; \
extern XRegister X##N;
AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS)
#undef DEFINE_REGISTERS
WRegister WSP(RegisterA64::kSPRegInternalCode);
XRegister SP(RegisterA64::kSPRegInternalCode);
XRegister IP0 = X16;
XRegister IP1 = X17;
XRegister LR = X30;
extern WRegister WSP;
extern XRegister SP;
extern XRegister IP0;
extern XRegister IP1;
extern XRegister LR;
//zero reg
XRegister XZR = X31;
WRegister WZR = W31;
extern XRegister XZR;
extern WRegister WZR;
extern RegisterA64 UnknowRegiser;
#define XReg(N) XRegister::get(N)
#define WReg(N) WRegister::get(N)
#endif //SANDHOOK_NH_REGISTER_LIST_A64_H
......@@ -48,6 +48,18 @@ namespace SandHook {
return getWide() == Reg128Bit;
}
virtual bool is(const Register &rhs) {
return rhs.code == code;
}
bool operator==(const Register &rhs) const {
return code == rhs.code;
}
bool operator!=(const Register &rhs) const {
return !(rhs == *this);
}
private:
U8 code;
};
......
......@@ -14,6 +14,11 @@ typedef uint16_t U16;
typedef uint32_t U32;
typedef uint64_t U64;
typedef int8_t S8;
typedef int16_t S16;
typedef int32_t S32;
typedef int64_t S64;
typedef size_t ADDR;
const int PTR_BYTE = sizeof(void*);
......
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