Commit cbbdfef6 authored by swift_gan's avatar swift_gan Committed by swift_gan

tweak sub/subs

parent b9946009
......@@ -462,15 +462,16 @@ void A64_MOV_REG::assembler() {
A64_SUBS_EXT_REG::A64_SUBS_EXT_REG() {}
A64_SUB_EXT_REG::A64_SUB_EXT_REG() {}
A64_SUBS_EXT_REG::A64_SUBS_EXT_REG(STRUCT_A64(SUBS_EXT_REG) &inst) : InstructionA64(&inst) {}
A64_SUB_EXT_REG::A64_SUB_EXT_REG(STRUCT_A64(SUB_EXT_REG) &inst) : InstructionA64(&inst) {}
A64_SUBS_EXT_REG::A64_SUBS_EXT_REG(RegisterA64 &rd, RegisterA64 &rn, const Operand &operand,
FlagsUpdate flagsUpdate) : rd(&rd), rn(&rn), operand(operand),
A64_SUB_EXT_REG::A64_SUB_EXT_REG(S s, RegisterA64 &rd, RegisterA64 &rn, const Operand &operand,
FlagsUpdate flagsUpdate) : s(s), rd(&rd), rn(&rn), operand(operand),
flagsUpdate(flagsUpdate) {}
void A64_SUBS_EXT_REG::decode(STRUCT_A64(SUBS_EXT_REG) *inst) {
void A64_SUB_EXT_REG::decode(STRUCT_A64(SUB_EXT_REG) *inst) {
s = S(inst->S);
if (inst->sf == 1) {
rd = XReg(static_cast<U8>(inst->rd));
rn = XReg(static_cast<U8>(inst->rn));
......@@ -485,8 +486,10 @@ void A64_SUBS_EXT_REG::decode(STRUCT_A64(SUBS_EXT_REG) *inst) {
operand.shift = Shift(inst->imm3);
}
void A64_SUBS_EXT_REG::assembler() {
SET_OPCODE(SUBS_EXT_REG);
void A64_SUB_EXT_REG::assembler() {
SET_OPCODE_MULTI(SUB_EXT_REG, 1);
SET_OPCODE_MULTI(SUB_EXT_REG, 2);
get()->S = s;
get()->sf = rd->isX() ? 1 : 0;
get()->option = operand.extend;
get()->imm3 = operand.shift;
......
......@@ -573,6 +573,7 @@ namespace SandHook {
class INST_A64(MOV_REG) : public InstructionA64<STRUCT_A64(MOV_REG)> {
public:
A64_MOV_REG();
A64_MOV_REG(STRUCT_A64(MOV_REG) &inst);
......@@ -593,25 +594,32 @@ namespace SandHook {
};
class INST_A64(SUBS_EXT_REG) : InstructionA64<STRUCT_A64(SUBS_EXT_REG)> {
class INST_A64(SUB_EXT_REG) : InstructionA64<STRUCT_A64(SUB_EXT_REG)> {
public:
A64_SUBS_EXT_REG();
A64_SUBS_EXT_REG(STRUCT_A64(SUBS_EXT_REG) &inst);
enum S {
Unsign = 0b0,
Sign = 0b1,
};
A64_SUB_EXT_REG();
A64_SUB_EXT_REG(STRUCT_A64(SUB_EXT_REG) &inst);
A64_SUBS_EXT_REG(RegisterA64 &rd, RegisterA64 &rn, const Operand &operand,
A64_SUB_EXT_REG(S s, RegisterA64 &rd, RegisterA64 &rn, const Operand &operand,
FlagsUpdate flagsUpdate);
DEFINE_IS(SUBS_EXT_REG)
DEFINE_IS_EXT(SUB_EXT_REG, TEST_INST_OPCODE(SUB_EXT_REG, 1) && TEST_INST_OPCODE(SUB_EXT_REG, 2))
DEFINE_INST_CODE(SUBS_EXT_REG)
DEFINE_INST_CODE(SUB_EXT_REG)
void decode(A64_STRUCT_SUBS_EXT_REG *inst) override;
void decode(A64_STRUCT_SUB_EXT_REG *inst) override;
void assembler() override;
public:
S s;
RegisterA64* rd;
RegisterA64* rn;
Operand operand = Operand();
......
......@@ -20,7 +20,7 @@ enum InstCodeA64 {
BR_BLR_RET,
CBZ_CBNZ,
TBZ_TBNZ,
SUBS_EXT_REG
SUB_EXT_REG
};
// Generic fields.
......
......@@ -200,14 +200,17 @@ DEFINE_STRUCT_A64(STR_UIMM) {
InstA64 size:2;
};
DEFINE_OPCODE(SUBS_EXT_REG, 0b1101011001)
DEFINE_STRUCT_A64(SUBS_EXT_REG) {
DEFINE_OPCODE(SUB_EXT_REG_1, 0b1)
DEFINE_OPCODE(SUB_EXT_REG_2, 0b01011001)
DEFINE_STRUCT_A64(SUB_EXT_REG) {
InstA64 rd:WideReg;
InstA64 rn:WideReg;
InstA64 imm3:3;
InstA64 option:3;
InstA64 rm:WideReg;
InstA64 opcode:10;
InstA64 opcode2:8;
InstA64 S:1;
InstA64 opcode1:1;
InstA64 sf:1;
};
......
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