Commit d72dc917 authored by swift_gan's avatar swift_gan Committed by swift_gan

add Exception Gen & SVC

parent cbbdfef6
......@@ -464,7 +464,9 @@ void A64_MOV_REG::assembler() {
A64_SUB_EXT_REG::A64_SUB_EXT_REG() {}
A64_SUB_EXT_REG::A64_SUB_EXT_REG(STRUCT_A64(SUB_EXT_REG) &inst) : InstructionA64(&inst) {}
A64_SUB_EXT_REG::A64_SUB_EXT_REG(STRUCT_A64(SUB_EXT_REG) &inst) : InstructionA64(&inst) {
decode(&inst);
}
A64_SUB_EXT_REG::A64_SUB_EXT_REG(S s, RegisterA64 &rd, RegisterA64 &rn, const Operand &operand,
FlagsUpdate flagsUpdate) : s(s), rd(&rd), rn(&rn), operand(operand),
......@@ -497,3 +499,32 @@ void A64_SUB_EXT_REG::assembler() {
get()->rn = rn->getCode();
get()->rd = rd->getCode();
}
A64_EXCEPTION_GEN::A64_EXCEPTION_GEN() {}
A64_EXCEPTION_GEN::A64_EXCEPTION_GEN(STRUCT_A64(EXCEPTION_GEN) &inst) : InstructionA64(&inst) {
decode(&inst);
}
A64_EXCEPTION_GEN::A64_EXCEPTION_GEN(A64_EXCEPTION_GEN::OP op, ExceptionLevel el, U16 imme) : op(
op), el(el), imme(imme) {}
void A64_EXCEPTION_GEN::decode(STRUCT_A64(EXCEPTION_GEN) *inst) {
op = OP(inst->op);
el = ExceptionLevel(inst->ll);
imme = static_cast<U16>(inst->imm16);
}
void A64_EXCEPTION_GEN::assembler() {
SET_OPCODE_MULTI(EXCEPTION_GEN, 1);
SET_OPCODE_MULTI(EXCEPTION_GEN, 2);
get()->op = op;
get()->ll = el;
get()->imm16 = imme;
}
A64_SVC::A64_SVC(U16 imme) : A64_EXCEPTION_GEN(XXC, EL1,imme) {}
......@@ -94,6 +94,13 @@ namespace SandHook {
LeaveFlags = 0
};
enum ExceptionLevel {
EL0 = 0b00,
EL1 = 0b01,
EL2 = 0b10,
EL3 = 0b11
};
class Operand {
public:
inline explicit Operand(){};
......@@ -626,6 +633,47 @@ namespace SandHook {
FlagsUpdate flagsUpdate;
};
class INST_A64(EXCEPTION_GEN) : public InstructionA64<STRUCT_A64(EXCEPTION_GEN)> {
public:
enum OP {
XXC = 0b000,
BRK = 0b001,
HLT = 0b010,
DCP = 0b101
};
A64_EXCEPTION_GEN();
A64_EXCEPTION_GEN(STRUCT_A64(EXCEPTION_GEN) &inst);
A64_EXCEPTION_GEN(OP op, ExceptionLevel el, U16 imme);
DEFINE_IS_EXT(EXCEPTION_GEN, TEST_INST_OPCODE(EXCEPTION_GEN, 1) && TEST_INST_OPCODE(EXCEPTION_GEN, 2))
DEFINE_INST_CODE(EXCEPTION_GEN)
void decode(A64_STRUCT_EXCEPTION_GEN *inst) override;
void assembler() override;
public:
OP op;
ExceptionLevel el;
U16 imme;
};
class INST_A64(SVC) : public INST_A64(EXCEPTION_GEN) {
public:
A64_SVC(U16 imme);
DEFINE_IS_EXT(EXCEPTION_GEN, TEST_INST_OPCODE(EXCEPTION_GEN, 1) && TEST_INST_OPCODE(EXCEPTION_GEN, 2) && TEST_INST_FIELD(op, XXC) && TEST_INST_FIELD(ll, EL1))
DEFINE_INST_CODE(SVC)
};
}
}
......
......@@ -20,7 +20,9 @@ enum InstCodeA64 {
BR_BLR_RET,
CBZ_CBNZ,
TBZ_TBNZ,
SUB_EXT_REG
SUB_EXT_REG,
EXCEPTION_GEN,
SVC
};
// Generic fields.
......
......@@ -214,5 +214,15 @@ DEFINE_STRUCT_A64(SUB_EXT_REG) {
InstA64 sf:1;
};
DEFINE_OPCODE(EXCEPTION_GEN_1, 0b11010100)
DEFINE_OPCODE(EXCEPTION_GEN_2, 0b11100100)
DEFINE_STRUCT_A64(EXCEPTION_GEN) {
InstA64 opcode1:8;
InstA64 op:3;
InstA64 imm16:16;
InstA64 opcode2:3;
InstA64 ll:2;
};
#endif //SANDHOOK_NH_INST_AARCH64_H
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